ADC Output Compression Using Sample Deltas for Pin-Limited Testing
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Solution Overview
Problem
Testing of analog-to-digital converters (ADCs) with a large number of data bits is inefficient due to the need for direct access and serial conversion, which increases test time and costs, and requires a large number of IC pins and automated test equipment.
Innovation Solution
Implementing a data compression procedure that shifts out the difference between consecutive samples, allowing for reduced pin usage while maintaining short test times, using N flip-flops to latch samples and a finite state machine to manage errors and serial output, effectively mapping 12-bit ADC data onto three pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial conversion is used to output ADC data, then the number of IC pins is reduced, but test time increases significantly
Solution Approach 1:
The 12-bit ADC data is segmented into two parts: 3 bits are output directly in parallel, while the remaining 9 bits are processed through a compression circuit that calculates differences between consecutive samples. This segmentation allows simultaneous parallel and compressed serial output, resolving the contradiction between pin reduction and test time.
Solution Approach 2:
The patent transitions from purely parallel output to a hybrid approach by introducing a temporal dimension through time-sequential sampling. The compression circuit processes samples over time, calculating differences between consecutive samples (a[i] - a[i-1]), which enables reduced pin count while maintaining acceptable test speeds through the time-multiplexed compression process.
2Measurement precision
If direct access to ADC with many data bits is implemented, then measurement accuracy is maintained, but testing cost and complexity increase
Solution Approach 1:
The patent extracts only the essential information needed for ADC testing by computing the difference between consecutive samples. Instead of directly accessing and testing all 12 bits, the system extracts the change information (delta) which contains the critical measurement data while reducing the bit width from 12 bits to 3 bits, thereby simplifying test equipment requirements while preserving measurement accuracy.
Solution Approach 2:
The patent changes the parameter representation from absolute ADC values to differential values (difference between consecutive samples). This parameter transformation reduces the data width from 12 bits to 3 bits while maintaining the ability to detect ADC errors and anomalies, thus reducing device complexity without sacrificing measurement precision.
3Loss of information
If 12-bit parallel output is used, then data accuracy is preserved, but the number of pins and test equipment required increases
Solution Approach 1:
The patent performs preliminary processing of the ADC data by pre-calculating the difference between consecutive samples within the device under test. This preliminary action of computing deltas before output reduces the data width from 12 bits to 3 bits, enabling pin reduction while preserving the essential information needed for accurate ADC characterization through the compressed differential representation.
Data Source
AI summary
A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.