Digital Circuit Testing TRIZ Cases

When reset cannot clear single event latch-up, watchdog-triggered power cycling restores microprocessor function and flags repeated failures.

Variably delayed sync pulses let a central device measure phase offsets and align distributed clocks despite path, temperature, and radiation effects.

A TDC-based evaluation circuit adjusts frequency and duty cycle so one test pattern can verify PLL-driven DUT functions across 312.5-3500 MHz.

Delayed clock and reference edge comparison enables real-time jitter detection with tunable timing thresholds to prevent signal-related system disruption.

Consecutive-sample delta compression lets high-bit ADC test data exit on fewer pins, cutting test time and equipment burden.

Backward bottleneck-ratio tracing pinpoints critical glitch sources in logic circuits, enabling incremental power analysis and gate adjustment.

Adjustable input and output delays let a comparison circuit check whether an IC meets timing, reducing test complexity and area.

Series timing cells combine delay and pulse-width adjustment to correct skew and place test-signal edges accurately across DUT channels.

Shared clock inverters and internal scan connections cut latch area and clock power while preserving LSSD testability and timing.

A target sampling signal stabilizes phase detection between high- and low-frequency clocks when filtering and pulse loss would otherwise cause errors.

Constant-step counter signals are checked in each clock domain using comparison and delay circuits to catch synchronization errors.

By aligning two clock signals within a noise window and alternating oscillation loops, this circuit measures jitter more precisely with controlled complexity.

PLL-based global time conversion keeps distributed inspection units synchronized over long distances, reducing clock jumps and drift.

Flip-flops and a multi-port delay line replace slow capacitor-based duty measurement, enabling faster clock analysis in less chip area.

A two-MOS and capacitor circuit replaces static current collection with voltage storage to simplify differential clock cross-point detection.

An on-chip MASH ΔΣ TDC measures PLL phase noise without high-speed probes or high-frequency clocks, improving stability and bandwidth.

Internal test signals delay clock and data paths to measure setup and hold times in directly attached 3D-IC dies with inaccessible pins.

Dynamic PMOS/NMOS calibration keeps resonant pulse timing accurate across PVT variation, improving on-chip clock reliability.

Converts PLL clock periods into pulse and code data to detect min-max jitter anomalies online before faults or transient noise cause failures.

Independent conversion paths and stored sensor characterization data let external devices verify results without adding multiple sensors.

Multiple independent noise paths, digital filters, and frequency compensation deliver well-defined SNR across aggregated wireless bandwidth.

Cross-coupled clock lines and a parallel latch-buffer layout cut metal congestion, resistance, and capacitance in scan test circuits.

Local ADC conversion at satellite monitors cuts analog routing noise and metal-layer use while scaling voltage and temperature sensing.

Iterative predistortion updates the signal generator input from measured spectra to suppress nonlinear distortion in high-frequency testing.

By combining voltage and current driver stages, this circuit reduces parasitic loading and improves pulse edge accuracy and bandwidth.

A scan chain links flip-flops and LUTs so OTP-based FPGAs can be tested and pattern-loaded before final memory programming.

Dynamic DMA-driven reconfiguration lets one PSoC chip program analog and digital blocks at runtime, cutting chip area and cost.

Built-in signal analysis and an embedded microcontroller let ASICs monitor internal logic in real time and reconfigure settings without slow sideband links.

Voltage droop is handled by monitoring supply variation and stretching only affected clock cycles so on-chip logic can finish reliably.

Replica delay paths measure each clock domain so an accelerated processor can assign finer speed bins and avoid one-speed limits across the chip.

An FPGA-based stimulus-response controller cuts handshaking delays in MTJ testing by generating, capturing, and analyzing waveforms locally.

Zero-crossing timing and correlation weighting improve dual-path amplifier gain calibration despite phase mismatch and DC offset.

Uses SerDes receiver pins for both scan-in and scan-out, enabling full chip scan-chain testing without dedicated test pins.

Delay-element clock generation replaces bulky DLL or PLL blocks to enable fast high-speed semiconductor testing with lower area and short locking time.

Delay circuits and alternating oscillation loops determine a noise window for accurate real-time jitter detection and clock correction.

Shared clock inverters and integrated LSSD scan cut latch area, clock capacitance, and power while supporting higher-frequency timing.

A flip-flop ring oscillator lets the output float at stop timing, preserving the latched state for accurate DRAM sensing time measurement.

An SR latch with a delay element decouples output timing from input pulse width, keeping one-shot pulses fixed even when inputs overlap.

A reference-free clock monitor uses cascaded flip-flops and delay elements to detect timing faults and tampering in ADAS circuits.

Software-controlled I/O channels switch between input, output, and multi-terminal measurement modes to cut interface clutter and keep control flexible.

Measures sub-clock delay by averaging uncorrelated signal transitions, improving timing accuracy despite delay-element tolerances.

By sharing clock and scan enable signals across cells, this flip-flop layout reduces external circuitry, power use, and memory array area.

A third-order MASH ΔΣ TDC converts PLL phase noise into a low-frequency digital signal, avoiding high-clock instability and costly probing.

A dual monitor tracks supply voltage and critical path delay to detect minimum operating voltage more accurately and reduce voltage margin.

Repeatedly shifting test pattern start times lets an ADC pinpoint the pattern segment that causes power droop and minimum voltage events.

Internal clock generation converts lower-frequency data clocks into matched high-speed signals, enabling precise semiconductor testing with existing equipment.

A flip-flop and delay-line scheme measures clock duty cycle faster than charge pumps while saving chip area and reducing noise.

An abnormality detection circuit drives the control terminal to a fault voltage, enabling compact oscillator fault notification without extra pins.

Faults are flagged by changing clock duty, amplitude, or frequency, letting external devices detect oscillator abnormalities without extra terminals.

A feedback flip-flop loop with swept oscillator input measures true logic-path maximum frequency without added mux delay.