Delay-Line Duty Cycle Measurement Circuit for Fast Clock Sampling
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Solution Overview
Problem
Conventional digital measurement circuits for clock duty cycle measurement are slow and reduce integration density due to the need for reduced current in charge pumps to minimize ripples, which increases measurement time and reduces chip space efficiency.
Innovation Solution
A digital measurement circuit using flip-flops, a multi-port delay line, and a multiplexer to measure clock pulse widths by delaying signals and comparing their rising and falling edges, allowing for high-speed duty cycle measurement in a compact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the current of the charge pump is reduced to minimize ripples, then the measurement accuracy is improved, but the measurement time increases
Solution Approach 1:
The patent replaces the conventional charge pump-based measurement system with a digital logic-based system using flip-flops, delay lines, and XOR gates. This substitution eliminates the need for charge pumps and capacitors, enabling fast measurement without ripples while maintaining high accuracy through digital signal processing and comparison techniques.
Solution Approach 2:
The patent changes the fundamental measurement parameter from voltage accumulation time (in charge pump systems) to signal propagation and comparison time (in digital logic systems). By measuring the time difference between rising and falling edges through digital delay lines and XOR gate operations, the system achieves both high speed and high accuracy without the trade-off present in conventional systems.
2Measurement precision
If the capacitance value of each capacitor is increased to reduce ripples, then the measurement accuracy is improved, but the area increases
Solution Approach 1:
The patent replaces the charge pump system with large capacitors with a compact digital logic system consisting of flip-flops, delay lines, and XOR gates. This substitution eliminates the need for large capacitors entirely, achieving high measurement accuracy through digital signal processing while occupying minimal chip area.
Solution Approach 2:
The patent uses digital delay lines to create multiple delayed copies of the input signal, which are then compared using XOR gates. This copying approach allows the system to measure duty cycle through logical comparison of signal timing rather than through physical capacitor charging, dramatically reducing the required chip area while maintaining measurement precision.
3Object-affected harmful factors
If the charge pump current is reduced to minimize ripples, then the noise is reduced, but the measurement speed decreases
Solution Approach 1:
The patent replaces the charge pump system that generates power supply noise with a digital logic system that operates on clocked signals. This substitution eliminates the noise generation inherent in charge pump operation while enabling high-speed measurement through synchronous digital logic operations and fast signal propagation through delay lines.
Solution Approach 2:
The patent uses periodic clock signals to control the flip-flops and synchronize the measurement process. This periodic action allows the system to perform measurements at high speed by sampling and comparing signals at defined clock edges, achieving both low noise (through synchronous operation) and high productivity (through fast clocked operations).
Data Source
AI summary
A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.