Circuit Speed Margin Detection Using Adjustable Delay Comparison
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Solution Overview
Problem
Conventional methods for detecting the operating speed of integrated circuits (ICs) are inefficient due to slow response times, high circuit area consumption, and complexity in determining dominant critical paths, making it difficult to accurately assess the margin of ICs under varying environmental and usage conditions.
Innovation Solution
A device comprising a signal generating circuit, adjustable delay circuits, a circuit under test (CUT), a comparison circuit, and a calibration circuit, which generates and delays input signals to determine if the CUT meets predetermined operation timing criteria, allowing for efficient detection of the margin and monitoring of IC speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional speed binning or adaptive voltage scaling techniques are used, then IC operating speed assessment is achieved, but the process requires complex PVTA analysis and multiple measurement conversions
Solution Approach 1:
The patent extracts the speed assessment function from complex PVTA analysis by introducing a dedicated test circuit that directly measures whether the CUT completes operations within a predetermined time window. This separates the speed measurement function from the complicated environmental parameter analysis, achieving accurate speed assessment without requiring complex voltage, temperature, or aging status measurements.
Solution Approach 2:
The patent introduces a test circuit as an intermediary between the CUT and the measurement system. This test circuit includes a signal generating circuit, delay circuits, and a comparison circuit that together mediate the speed measurement process, converting the complex PVTA-dependent speed characterization into a simple time-window completion check that can be directly measured.
2Measurement precision
If ring oscillator technique is used to estimate operating speed, then speed measurement is achieved, but response time is slow and voltage variation cannot be measured within short period
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the predetermined time window threshold in the test circuit before actual speed measurements are taken. The comparison circuit is pre-configured with this threshold, allowing immediate comparison and decision-making during operation without requiring real-time complex calculations or waiting for oscillator stabilization, thus achieving fast response time while maintaining measurement accuracy.
3Measurement precision
If voltage meter or temperature meter technique is used, then operating speed estimation is achieved, but circuit area consumption is high and conversion to operating speed is required
Solution Approach 1:
The patent extracts only the essential timing measurement function needed for speed assessment, eliminating the need for separate voltage and temperature measurement circuits. The test circuit directly measures whether the CUT completes its operation within the predetermined time window, providing speed estimation without requiring large-area voltage or temperature meters and their subsequent conversion processes.
4Measurement precision
If critical path monitoring technique is used, then operating speed measurement is achieved, but design flow becomes complicated and not all critical paths can be monitored
Solution Approach 1:
The patent creates a universal test circuit that can measure the operating speed of any CUT regardless of its specific critical path characteristics. The test circuit generates a start signal, applies it to the CUT, and measures whether the CUT completes its operation within the predetermined time window. This universal approach eliminates the need for complex, circuit-specific critical path identification and monitoring designs.
Data Source
AI summary
Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.