Clock Generation Circuit for High-Speed Semiconductor Testing
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Solution Overview
Problem
High-speed semiconductor testing requires expensive test equipment that cannot keep pace with the rapid development of semiconductor apparatuses, necessitating a method to perform accurate tests using relatively poor test equipment.
Innovation Solution
A semiconductor apparatus with a clock generation circuit that receives data clock signals of different frequencies and generates internal clock signals with the same frequency and phase difference in both operation modes, allowing for precise data input/output operations even with high-frequency clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test equipment is upgraded to provide high-speed clock signals for accurate testing, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
The semiconductor apparatus generates its own internal clock signals from the external data clock signals received through the pad structure. The clock generation circuit inside the semiconductor apparatus converts the external clock signals into internal clock signals with appropriate frequencies and phase relationships, making the system self-sufficient for high-speed testing without requiring expensive external high-speed clock signal generators
Solution Approach 2:
The patent changes the frequency parameters of clock signals by using different operation modes (first operation mode and second operation mode) that generate internal clock signals at different frequencies. The clock generation circuit can generate internal clock signals at a first frequency in the first operation mode and at a second frequency in the second operation mode, allowing flexible adaptation to different testing requirements while using the same test equipment
2Productivity
If clock signal frequency increases to match semiconductor operating speed, then productivity improves, but measurement precision deteriorates due to limitations of existing test equipment
Solution Approach 1:
The patent introduces an intermediary clock generation circuit that acts as a bridge between the external test equipment and the internal high-speed logic circuits. This circuit receives lower-frequency data clock signals from the external apparatus and generates higher-frequency internal clock signals with precise phase relationships, enabling high-speed testing without requiring the external test equipment to operate at the same high frequencies
Solution Approach 2:
The patent segments the clock signal generation function into two parts: the external apparatus provides data clock signals at one frequency, and the internal clock generation circuit generates internal clock signals at a different, higher frequency. This segmentation allows each part to operate at optimal frequencies, with the external apparatus using lower frequencies it can provide accurately and the internal circuit generating the high frequencies needed for high-speed operation
3Device complexity
If single clock signal is used for data operations, then device complexity reduces, but manufacturing precision suffers due to insufficient phase control
Solution Approach 1:
The patent segments the clock signal into multiple phase components by generating first internal clock signals and second internal clock signals with a phase difference (e.g., 90 degrees). These segmented clock signals are used for different data operations (read and write), providing precise phase control for each operation type without requiring a single complex clock signal
Solution Approach 2:
The patent makes the clock generation circuit multi-functional by enabling it to generate different frequencies and phase relationships based on operation modes. The same clock generation circuit can generate internal clock signals at a first frequency in the first operation mode and at a second frequency in the second operation mode, providing universal functionality for different testing scenarios
Data Source
AI summary
A semiconductor apparatus may be provided. The semiconductor apparatus may include a clock generation circuit. The clock generation circuit may be configured to receive data clock signals and generate internal clock signals in both a first and second operation mode.