FPGA Scan Chain Testing for OTP Memory Configuration
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) with one-time programmable (OTP) memory configurations face challenges in pre-programming circuit operation testing and data writing during the test stage, as OTP memory limits the ability to check circuit operations and write test patterns.
Innovation Solution
The integration of a logic block with a look-up table circuit, selection circuits, flip-flops, and a switch block that allows for switching wiring lines based on input signals, enabling both normal and test mode operations, and a test method that forms a scan chain to connect flip-flops to LUT circuits for comprehensive pattern testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If OTP memory is used in switch blocks, then manufacturing precision and reliability are improved, but ease of operation deteriorates because circuit operation cannot be checked before programming and test patterns cannot be written during test stage
Solution Approach 1:
The patent applies preliminary action by forming a scan chain connection between flip-flops and LUT circuits during the test stage before final programming. This allows test patterns to be written and circuit operations to be checked prior to committing data to the OTP memory, thereby resolving the contradiction between manufacturing precision and ease of operation.
2Device complexity
If OTP memory is used in switch blocks, then device complexity is reduced, but adaptability deteriorates because no additional data can be written after test stage
Solution Approach 1:
The scan chain enables preliminary testing and validation before final data commitment to OTP memory. This preliminary action phase provides the adaptability needed for test pattern writing and circuit verification, while the OTP memory itself maintains its simplicity and reduced complexity for final operation.
Data Source
AI summary
An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.