On-Chip MASH ΔΣ TDC for Stable PLL Phase Noise Measurement
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Solution Overview
Problem
Current methods for measuring phase noise in phase-locked loops (PLLs) are costly and complex, and high-speed probes face contact issues at high temperatures, while existing built-in self-test (BIST) circuits suffer from stability issues due to high-frequency input clocks, making them unsuitable for general PLL applications.
Innovation Solution
A high-order delta sigma (ΔΣ) time-to-digital converter (TDC) architecture, specifically a MASH type third-order ΔΣ TDC, is implemented on-chip, which includes a timing generator, phase detector, charge pump, voltage-controlled delay line (VCDL), and 1-bit TDC, converting phase noise into a low-frequency digital signal without requiring high-frequency reference clocks, thus avoiding stability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-order continuous time ΔΣ modulators are used to measure PLL in-band phase noise, then measurement precision is improved, but stability deteriorates due to stability issues
Solution Approach 1:
The patent divides the high-order continuous time ΔΣ modulator into multiple cascaded lower-order modulators (typically three first-order modulators for a third-order system). Each stage processes the signal independently and contributes to the overall noise shaping function, avoiding the stability issues inherent in monolithic high-order designs while maintaining the measurement precision benefits of high-order noise shaping.
Solution Approach 2:
The patent implements feedback mechanisms within each cascaded modulator stage to ensure stability. The feedback loops in the charge pump and phase detector stages allow each individual modulator to remain stable while collectively achieving the desired third-order noise shaping performance for accurate phase noise measurement.
2Stability of the object's composition
If clock rate is increased to 340 MHz to avoid stability issues, then stability is improved, but adaptability deteriorates because high frequency input clock is not suitable for general PLL applications
Solution Approach 1:
The patent changes the architectural parameters of the ΔΣ modulator from a single high-frequency clocked stage to multiple cascaded lower-frequency stages. This parameter change allows the system to operate at lower, more versatile clock frequencies suitable for general PLL applications while maintaining stability through the distributed architecture of multiple interconnected stages.
3Ease of manufacture
If 2nd-order ΔΣ TDC structures are used, then ease of manufacture is improved, but measurement precision deteriorates due to limited noise shaping capabilities
Solution Approach 1:
The patent merges three first-order ΔΣ modulator stages into a unified third-order MASH architecture. This combination achieves superior noise shaping capabilities and measurement precision compared to second-order systems, while the modular nature of cascading identical first-order stages maintains ease of manufacture and design scalability.
Data Source
AI summary
An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).