Multi-Bit Scan Latches With Shared Clocking for Lower Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern microprocessors and digital signal processors face challenges in reducing silicon cost, PCB footprint, and power consumption due to the large area and power consumption of standard cell latches and flip-flops with Level-Sensitive Scan Design (LSSD), which also complicates the integration of time-borrowing flip-flops for improved frequency and timing performance.
Innovation Solution
The integration of multi-bit latches and flip-flops with LSSD scan using shared local clock inverters and internal connections reduces unnecessary transistors and clock pin capacitance, and the adoption of time-borrowing vectored flip-flops with shared clocking circuitry amortizes clock power overhead across bits, allowing for area-efficient design and reduced dynamic power costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSSD scan circuitry is integrated into standard cell latches and flip-flops, then testability is improved, but area consumption increases significantly
Solution Approach 1:
The patent merges LSSD scan circuitry with standard cell latches and flip-flops into a unified structure. The scan circuitry is integrated directly into the latch/flip-flop cell, eliminating the need for separate scan cells and reducing overall area consumption while maintaining full testability functionality.
Solution Approach 2:
The patent creates a universal latch/flip-flop cell that can operate in both normal mode (for functional operation) and scan mode (for testing). The same physical cell structure supports multiple functions through control signals, eliminating the need for separate test cells and reducing area overhead.
2Reliability
If LSSD scan circuitry is added to each latch, then scan capability is improved, but power consumption increases due to additional clock pin capacitance
Solution Approach 1:
The patent combines scan circuitry with the main latch/flip-flop cell, allowing shared clocking resources. By integrating scan functionality into the existing cell structure, the patent reduces the number of separate clock pins and their associated capacitance, thereby reducing dynamic power consumption during scan operations.
3Speed
If time-borrowing flip-flops are used to improve frequency and timing performance, then speed is improved, but area consumption increases
Solution Approach 1:
The patent integrates time-borrowing functionality directly into the vectored latch/flip-flop cell structure. By combining the time-borrowing mechanism with the existing cell architecture rather than adding it as a separate component, the patent achieves improved frequency and timing performance while minimizing area overhead.
4Use of energy by moving object
If multi-bit latches with shared clock inverters are used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple latch/flip-flop cells into a vectored structure with shared clock inverters. This consolidation reduces the total number of clock inverters needed, thereby reducing dynamic power consumption during clock distribution while the modular vectored structure keeps the increased complexity manageable.
Data Source
AI summary
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.