PLL Phase Noise BIST Using a MASH ΔΣ Time-to-Digital Converter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for measuring phase noise in phase-locked loops (PLLs) are costly and complex, and high-speed probes face contact issues at high temperatures, while existing built-in self-test (BIST) circuits suffer from stability issues due to high-frequency input clocks, making them unsuitable for general PLL applications.
Innovation Solution
A high-order delta sigma (ΔΣ) time-to-digital converter (TDC) architecture, specifically a MASH type third-order ΔΣ TDC, is implemented on-chip, which includes a timing generator, phase detector, charge pump, voltage-controlled delay line, and 1-bit TDC, converting phase noise into a low-frequency digital signal without requiring high-frequency reference clocks, thus avoiding stability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed probes are used for phase noise measurement, then measurement accuracy is improved, but contact reliability deteriorates at high temperatures
Solution Approach 1:
The system uses self-service by implementing a built-in self-test (BIST) circuit that performs phase noise measurements internally without requiring external high-speed probes. The on-chip TDC and ΔΣ modulator enable the PLL to measure its own phase noise, eliminating contact reliability issues while maintaining measurement accuracy.
2Measurement precision
If 2nd-order delta sigma TDC is used for phase noise measurement, then noise shaping capability is improved, but device complexity increases
Solution Approach 1:
The system segments the phase noise measurement function into modular on-chip components: a phase detector, charge pump, voltage-controlled delay line, 1-bit TDC, and ΔΣ modulator. This segmentation achieves effective noise shaping while managing complexity through functional decomposition and integration.
3Productivity
If high frequency input clock is used for PLL BIST, then measurement bandwidth is improved, but circuit stability deteriorates
Solution Approach 1:
The system changes the operating parameters by using a low-frequency input clock (e.g., 10 MHz) instead of high-frequency clocks, while achieving wide measurement bandwidth through the ΔΣ modulator's noise shaping capability. This parameter change resolves the stability issue while maintaining measurement effectiveness.
4Measurement precision
If high order continuous time delta sigma modulator is used, then noise shaping performance is improved, but circuit stability deteriorates
Solution Approach 1:
The system uses a simple 1-bit TDC and 2nd-order continuous time ΔΣ modulator instead of complex high-order modulators. This approach achieves sufficient noise shaping performance with significantly improved stability, avoiding the stability issues inherent in high-order continuous time ΔΣ modulators.
Data Source
AI summary
An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).