Multi-Bit LSSD Sequential Circuit With Shared Clocking
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Solution Overview
Problem
Modern microprocessors and digital signal processors face challenges in reducing silicon cost, PCB footprint, and power consumption due to the large area and power consumption of standard cell latches and flip-flops with Level-Sensitive Scan Design (LSSD), which also complicates the integration of time-borrowing flip-flops for improved frequency and timing performance.
Innovation Solution
The integration of multi-bit latches and flip-flops with LSSD scan using shared local clock inverters and internal connections reduces unnecessary transistors and clock pin capacitance, while time-borrowing vectored flip-flops with shared clocking circuitry amortize clock power overhead and fit within the same layout area, enabling easier insertion during design or debug modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSSD scan circuits are added to standard cell latches, then testability is improved, but area consumption increases significantly (70% of standard cell size)
Solution Approach 1:
The patent combines multiple latches into a multi-bit latch structure where LSSD scan circuits are shared across multiple bits. The scan input, scan output, and scan control signals are common to all bits, eliminating redundant scan circuitry. This merging approach maintains full testability while reducing the overall area consumption compared to having separate LSSD circuits for each latch.
Solution Approach 2:
The multi-bit latch structure implements universal scan circuitry that serves all bits simultaneously. The single scan input can load data into multiple bits, and the single scan output can read from multiple bits, making the scan system multi-functional. This universality reduces the area overhead while preserving testability across the entire multi-bit structure.
2Speed
If time-borrowing flip-flops are integrated for improved frequency and timing performance, then speed is improved, but device complexity increases
Solution Approach 1:
The time-borrowing flip-flop is segmented into master and slave latches with distinct clock phases. The master latch captures data during one clock phase while the slave latch prepares for the next phase. This segmentation allows independent optimization of each latch, simplifying the overall design while achieving time-borrowing functionality for improved frequency operation.
Solution Approach 2:
The patent implements dynamic clocking where the slave latch clock is derived from the master latch clock with a phase shift. This dynamic relationship allows the flip-flop to borrow time from one phase to meet setup requirements in the next phase, improving maximum operating frequency without requiring a completely redesign of the basic flip-flop structure.
3Use of energy by stationary object
If multi-bit latches with shared clock inverters are used, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple latches share common clock inverters and clock distribution networks, consolidating the clocking infrastructure. Instead of having separate clock inverters for each latch, the multi-bit structure uses a unified clock network that serves all bits, significantly reducing the total number of clock inverters and their associated power consumption.
Solution Approach 2:
The patent implements local clock buffering where clock signals are inverted and distributed locally to each bit within the multi-bit latch. This local quality approach ensures that each bit receives a properly timed clock signal while sharing the overall clock infrastructure, balancing power reduction with the need for precise timing control across different regions of the cell.
Data Source
AI summary
An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.