Logic Path Measurement Circuit for Exact Maximum Frequency
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Solution Overview
Problem
Existing measurement devices for logic paths in microelectronics fail to accurately determine maximum frequencies due to unnecessary delays caused by extra components like multiplexers and the exclusion of flip flop intrinsic delay and setup time in frequency measurements.
Innovation Solution
A measurement circuit that includes a flip flop device with a logic path looping its output signal back to itself, utilizing a voltage-controlled oscillator to vary the input signal frequency, allowing for the determination of maximum frequency by altering the frequency ratio from 1/2 to 1/4, thereby accounting for intrinsic delay and setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiplexers and buffer loading caps are added to measure critical path delay, then measurement capability is provided, but unnecessary delays are introduced that reduce measurement accuracy
Solution Approach 1:
The patent removes multiplexers and buffer loading caps from the measurement circuit to eliminate unnecessary delays. The measurement is performed directly through the logic path without intermediate components that would add extraneous delay, thereby improving measurement accuracy of maximum frequency.
Solution Approach 2:
The measurement circuit is segmented into distinct functional blocks: a first logic path for signal transmission, a second logic path for feedback, and a buffer isolated from the critical measurement path. This segmentation allows the measurement to occur through pure logic paths without contamination from buffer delays.
2Measurement precision
If flip flop intrinsic delay and setup time are excluded from frequency measurement, then measurement simplicity is maintained, but accurate maximum frequency cannot be determined
Solution Approach 1:
The patent employs a feedback mechanism where the output of the D flip-flop is fed back to its own D input through the logic path under test. This creates a loop that allows measurement of the maximum frequency including the flip-flop's intrinsic delay and setup time, as the signal must successfully traverse the entire path including the flip-flop boundaries.
Solution Approach 2:
The measurement circuit merges the flip-flop intrinsic delay and setup time into the measurement path by directly connecting the flip-flop output back to its input through the logic path. This integration ensures that the maximum frequency measurement inherently includes these critical timing parameters without requiring separate measurement circuits.
3Measurement precision
If known measurement devices are used, then measurement functionality is provided, but exact maximum frequency of logic path cannot be measured due to missing flip flop intrinsic delay
Solution Approach 1:
The patent uses a dynamic measurement approach where the clock frequency is swept across a range of values to identify the maximum frequency at which the feedback loop remains stable. This dynamic sweeping method captures the actual maximum operating frequency including all intrinsic delays and setup times, providing a reliable representation of the logic path's true performance capability.
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to measurement circuits for logic paths and methods of manufacture. The circuit includes: a flip flop device outputting an output signal comprising an intrinsic delay; a logic path looping the output signal back to the flip flop device such that the intrinsic delay is to be received by the flip flop device; and an oscillator which feeds an input signal into the logic path and sweeps the input signal to alter the looped output signal thereby providing a maximum frequency of the logic path.