Auto-Calibrated Pulse Generator for PVT-Stable Resonant Timing
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Solution Overview
Problem
Current digital circuits face challenges in maintaining accurate on-chip timing and clocking due to variations in physical and electrical properties, leading to potential malfunctions and data loss, especially in MOS/VLSI technology where uniformity in clock and signal timing generation is difficult to achieve.
Innovation Solution
An auto-calibration circuit is introduced, comprising an inverter block, gated inverters, comparators, PMOS and NMOS counters, and a voltage divider, which calibrates the circuit by adjusting the number of PMOS and NMOS transistors based on input signals and voltage thresholds to maintain precise timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog checking is used periodically to verify timing accuracy, then timing verification is achieved, but timing accuracy cannot be continuously maintained
Solution Approach 1:
The patent implements a feedback mechanism where the output of the XOR gate is fed back to control the counters, which in turn adjust the pulse width. This closed-loop feedback system continuously monitors and corrects timing deviations, ensuring continuous timing accuracy rather than periodic checking.
Solution Approach 2:
The circuit is self-calibrating through the automatic adjustment mechanism. The XOR gate detects timing errors and the counters automatically adjust the pulse width without external intervention, making the system self-correcting and maintaining continuous timing accuracy autonomously.
2Measurement precision
If complex timing interface circuitry is employed to verify clocking accuracy, then timing verification capability is improved, but device complexity increases
Solution Approach 1:
The patent combines the verification and adjustment functions into a single integrated circuit block. The XOR gate, counters, and pulse generator work together as one unified system, eliminating the need for separate complex timing interface circuitry while maintaining verification capability.
Solution Approach 2:
The circuit performs self-verification and self-adjustment without requiring external complex timing interface circuitry. The XOR gate automatically detects timing errors and the counters self-correct the pulse width, simplifying the overall system architecture.
3Manufacturing precision
If the number of PMOS and NMOS transistors is fixed, then device simplicity is maintained, but timing accuracy cannot be adjusted for process variations
Solution Approach 1:
The patent makes the transistor count dynamic by using counters that can adjust the number of PMOS and NMOS transistors activated in the pulse generator. This dynamic configuration allows the circuit to adapt to process variations and maintain timing accuracy without requiring multiple fixed configurations.
Solution Approach 2:
The circuit changes the parameter of transistor count dynamically through the counter adjustment mechanism. By varying the number of active transistors based on timing error detection, the system achieves precise timing control while maintaining a relatively simple base circuit structure.
Data Source
AI summary
Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level.