Clock Generation Circuit Using Delay Elements for Fast Frequency Scaling
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Solution Overview
Problem
Current semiconductor testers struggle to keep pace with the increasing operation speed of semiconductor devices, as they often cannot generate signals above 200 MHz, necessitating the use of frequency multiplying circuits like DLL or PLL, which require a wide area, long locking times, and complex implementations.
Innovation Solution
A clock generation circuit that includes a frequency detector, control signal generator, and period controller, using first and second unit delayers to generate an internal clock and output clock based on a target frequency, allowing for efficient high-speed testing with a simple structure and short locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL or PLL circuit is used for frequency multiplication, then stable operation and duty ratio compensation are achieved, but area occupancy increases and locking time becomes long
Solution Approach 1:
The frequency multiplication function is segmented into multiple independent delay elements connected in series, where each element contributes a specific delay amount. This segmentation allows the total delay to be distributed across multiple small units rather than requiring a single large DLL/PLL circuit, thereby reducing area occupancy while maintaining stable operation through the cumulative delay effect.
Solution Approach 2:
The circuit uses controllable delay elements that can dynamically adjust their delay amounts based on control signals. This dynamic capability allows the system to achieve frequency multiplication without requiring the complex feedback and locking mechanisms of traditional DLL/PLL circuits, reducing area while maintaining stability through controlled delay adjustment.
2Reliability
If DLL or PLL circuit is used for frequency multiplication, then stable operation is achieved, but locking time becomes long
Solution Approach 1:
The delay elements are pre-configured with specific delay characteristics during circuit design and fabrication. When operation begins, the appropriate delay elements are simply enabled through control signals without requiring the gradual phase adjustment and locking process that DLL/PLL circuits need, thereby eliminating locking time while maintaining stable operation through pre-established delay relationships.
Solution Approach 2:
The circuit skips the traditional locking process by directly enabling the required number of delay elements to achieve the desired frequency multiplication. This rushing through of the frequency establishment process eliminates the time-consuming locking phase while the stable operation is maintained through the inherent stability of the delay element chain.
3Reliability
If DLL or PLL circuit is used for frequency multiplication, then duty ratio compensation is achieved, but device complexity increases
Solution Approach 1:
The frequency multiplication and duty ratio adjustment functions are merged into a single structure of delay elements. By controlling the number and configuration of delay elements, both frequency multiplication and duty ratio optimization are achieved simultaneously without requiring separate DLL/PLL circuits for each function, thereby reducing overall device complexity while maintaining both capabilities.
Solution Approach 2:
The delay element chain serves multiple functions: frequency multiplication, duty ratio adjustment, and potential frequency division. This multi-functionality eliminates the need for separate dedicated circuits for each operation, reducing device complexity while maintaining the ability to perform duty ratio compensation and stable operation across different modes.
4Productivity
If frequency multiplying circuit is used for high-speed testing, then testing capability matches device speed, but area occupancy and complexity increase
Solution Approach 1:
The circuit achieves high testing speed capability by changing the effective delay parameter through control signals that enable or disable specific delay elements. By adjusting the total delay through parameter control rather than through complex frequency synthesis, the system achieves high-speed testing capability with minimal area occupancy compared to traditional frequency multiplying circuits.
Data Source
AI summary
A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.