SR Latch One-Shot Circuit for Fixed Output Pulse Width
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Solution Overview
Problem
One-shot circuits using AND gates face issues where output pulse width tracks input pulse width, leading to inconsistent output pulse duration and edge shifting when faced with varying input pulse widths, especially when input pulses overlap or have different widths.
Innovation Solution
The implementation of a set-reset (SR) latch with a delay element and adjustable non-inverting delay buffers or inverters to produce a controlled output pulse of fixed duration, independent of input pulse widths, ensuring the output pulse width remains constant regardless of input variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an AND gate is used to implement a one-shot circuit, then the circuit structure is simple, but the output pulse width tracks the input pulse width instead of staying constant
Solution Approach 1:
The patent introduces an SR latch as an intermediary component between the AND gate and the output. The SR latch receives the AND gate output and uses it to set the output pulse duration independently of the input pulse width. The delay element also acts as an intermediary, inserting a fixed time delay that determines the output pulse width, effectively decoupling the output duration from the input pulse characteristics.
Solution Approach 2:
The delay element performs a preliminary action by introducing a predetermined time delay in the reset signal path. This delay is established before the output pulse generation, ensuring that the output pulse width is determined by the delay element's characteristics rather than by variations in the input pulse width. The SR latch is also prepared in advance to respond to the delayed reset signal.
2Reliability
If the input pulse width varies, then the one-shot circuit should maintain constant output pulse width, but the output pulse front edge shifts and width tracks the input pulse width
Solution Approach 1:
The SR latch acts as a mediator that decouples the timing relationship between input and output pulses. By using the SR latch to control the output based on a delayed version of the input signal, the circuit maintains consistent output pulse width and timing independent of input pulse variations. The delay element serves as another intermediary that establishes a fixed temporal relationship.
Solution Approach 2:
The patent changes the parameter control mechanism by using the delay element's fixed delay parameter to determine output pulse width, rather than allowing the input pulse width parameter to control it. This parameter transformation ensures that output pulse characteristics remain constant despite variations in input pulse parameters.
3Stability of the object's composition
If a downward pulse preceding the input pulse is shorter than the nominal output pulse width, then the output pulse front edge should remain stable, but it shifts out and width tracks the downward pulse width
Solution Approach 1:
The delay element provides preliminary anti-action by ensuring that the reset signal is delayed sufficiently to prevent premature termination of the output pulse. This predetermined delay counteracts the effect of short downward pulses that would otherwise cause the output pulse front edge to shift and width to track the downward pulse width.
Solution Approach 2:
The SR latch mediates between the input signal and output pulse, using the delayed reset signal to control the output duration. This mediation ensures that the output pulse characteristics are determined by the delay element rather than by variations in preceding downward pulses, maintaining front edge stability and consistent width.
Data Source
AI summary
An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.