MTJ Electrical Testing Circuit for Faster Stimulus-Response Analysis
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Solution Overview
Problem
Current magnetic electrical test apparatuses for magnetic tunnel junction devices suffer from slow execution times due to communication handshaking between the computer and digitizer, leading to increased processing and memory requirements for handling large numbers of waveform patterns, which hampers rapid analysis and decision-making during electrical evaluation.
Innovation Solution
A stimulus/response controller is introduced, equipped with a configurable function circuit and communication interface, allowing for the generation of stimulus signals, capture of response signals, and performance of analytical operations prior to transmission, thereby minimizing processing and communication overhead. This controller includes features like response pulse averaging, differential resistance calculation, and bit error rate determination, enabling quick analysis and efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If communication handshaking between computer and digitizer is used for electrical testing, then measurement precision is maintained, but execution time increases and productivity decreases
Solution Approach 1:
The system segments the testing functions by separating the digitizer from the computer and introducing an FPGA-based controller that can independently generate stimulus signals and capture responses. This segmentation eliminates the need for continuous computer-digitizer communication handshaking, allowing parallel operation of signal generation, acquisition, and processing functions.
Solution Approach 2:
The patent introduces an FPGA-based stimulus/response controller as an intermediary between the computer and digitizer. This intermediary handles real-time stimulus signal generation and response capture locally, reducing communication overhead and enabling faster execution while maintaining measurement precision through dedicated hardware processing.
2Reliability
If large numbers of waveform patterns are processed through computer communication, then comprehensive testing is achieved, but processing overhead and memory requirements increase
Solution Approach 1:
The system performs preliminary actions by pre-loading stimulus patterns into the FPGA controller's memory before testing begins. This allows the controller to autonomously generate and process multiple waveform patterns without real-time computer intervention, reducing processing overhead and memory requirements during actual testing operations.
Solution Approach 2:
The patent replaces the mechanical communication handshaking system between computer and digitizer with an electronic FPGA-based control system. This substitution enables parallel processing of multiple waveform patterns through hardware logic, significantly reducing processing overhead and memory requirements while maintaining comprehensive testing capability.
3Loss of time
If real-time analysis is performed during electrical evaluation, then rapid decision-making is enabled, but processing resources and communication bandwidth are consumed
Solution Approach 1:
The FPGA-based stimulus/response controller acts as an intermediary that performs real-time analysis of captured responses locally. By processing data at the edge device rather than transmitting all raw data to the computer for analysis, the system enables rapid decision-making while minimizing consumption of processing resources and communication bandwidth.
Solution Approach 2:
The system implements self-service by enabling the FPGA controller to autonomously perform stimulus generation, response capture, and preliminary analysis functions. This self-sufficient operation reduces the need for continuous computer processing resources and minimizes communication bandwidth consumption, as only essential results need to be transmitted to the host system.
Data Source
AI summary
A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.