Digital Duty-Cycle Measurement Circuit Using Flip-Flops and Delay Lines
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Solution Overview
Problem
Conventional digital measurement circuits for clock duty cycle measurement are slow and reduce integration density due to the need for large capacitors to minimize voltage ripples, which increases measurement time and reduces chip space efficiency.
Innovation Solution
A digital measurement circuit using flip-flops and a multi-port delay line to measure clock pulse widths by delaying signals and comparing their rising and falling edges, allowing for high-speed duty cycle measurement in a compact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the capacitance value of each capacitor is increased to minimize voltage ripples, then the measurement accuracy is improved, but the area occupied increases and integration density is reduced
Solution Approach 1:
The patent replaces the conventional charge pump circuit with capacitors and comparators with a digital measurement circuit using flip-flops and delay lines. This substitution eliminates the need for large capacitors while achieving accurate duty cycle measurement through digital timing methods, thereby reducing occupied area while maintaining measurement precision.
2Measurement precision
If the current of the charge pump is reduced to minimize voltage ripples, then the measurement accuracy is improved, but the measurement time increases
Solution Approach 1:
The patent replaces the slow charge pump charging/discharging process with a fast digital timing method using flip-flops that capture clock edges. This digital approach eliminates the time-consuming capacitor charging process while maintaining measurement accuracy, thereby reducing measurement time significantly.
Solution Approach 2:
The patent uses delay lines to pre-generate multiple delayed versions of the clock signal before sampling. This preliminary action allows the sampling flip-flops to directly capture the duty cycle information without waiting for capacitor voltages to converge, thereby reducing measurement time while maintaining accuracy.
3Measurement precision
If the capacitance value of each capacitor is increased to minimize voltage ripples, then the measurement accuracy is improved, but the integration density is reduced
Solution Approach 1:
The patent replaces the analog capacitor-based measurement system with a digital system using flip-flops and delay lines. This substitution eliminates the need for large capacitors, thereby maintaining high integration density while achieving accurate duty cycle measurement through digital timing and sampling methods.
4Measurement precision
If conventional charge pump method is used to measure duty, then the measurement can be performed, but the measurement speed is slow
Solution Approach 1:
The patent replaces the slow charge pump charging process with fast digital logic operations. The sampling flip-flops capture the duty cycle information directly from delayed clock signals in a single clock cycle, eliminating the time-consuming capacitor charging and voltage convergence process, thereby achieving high-speed duty measurement while maintaining accuracy.
Data Source
AI summary
A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.