Deserializer Port Scan-Chain Testing Without Extra Chip Pins
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Solution Overview
Problem
Existing semiconductor chip designs face challenges in performing adequate scan testing due to the limited availability of pins for serializer/deserializer (SerDes) blocks, which are often used for high-bandwidth communications, leaving insufficient pins for scan chain testing.
Innovation Solution
The implementation of a deserializer port with a serial-to-parallel converter and scan-chain test logic circuit that allows for concurrent input and output of test data streams on the SerDes receiver pins, enabling effective scan-chain testing without interfering with the serializer functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple SerDes blocks are employed for high bandwidth communications, then communication bandwidth is improved, but the number of available pins for scan chain testing decreases
Solution Approach 1:
The SerDes receiver pins are configured to perform dual functions: serving as communication interfaces for high-bandwidth data reception and as scan chain test interfaces for loading test vectors and retrieving test results. The deserializer block is selectively activated to receive either communication data or scan chain test data through the same physical pins, eliminating the need for separate dedicated test pins.
2Adaptability or versatility
If SerDes driver pins are used for scan-out data transmission, then pin utilization is improved, but scan testing coverage of the serializer block becomes inadequate
Solution Approach 1:
Instead of using the serializer output pins (driver pins) for scan-out as in conventional approaches, the invention inverts the approach by using the deserializer input pins (receiver pins) for both scan-in and scan-out operations. The scan chain test results are loaded back through the same receiver pins using the deserializer block, ensuring that the serializer block itself can be properly tested while maintaining high pin utilization.
3Ease of operation
If dedicated scan chain pins are provided separate from SerDes pins, then scan testing capability is improved, but the number of pins required increases
Solution Approach 1:
The receiver pins are designed to universally handle both normal communication reception and scan chain testing operations. During test mode, the deserializer block is configured to receive scan chain test vectors and pass them to the scan chain logic, while during normal operation, the same pins receive communication data. This multi-functionality eliminates the need for separate dedicated test pins.
Data Source
AI summary
Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.