Multi-Clock Domain Signal Verification for Constant-Step Counters
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Solution Overview
Problem
Electronic devices with multiple clock domains face challenges in accurately transmitting and verifying signals comprising successive numbers separated by a constant value, particularly due to errors caused by bit value changes across different clock frequencies.
Innovation Solution
A device comprising a first circuit that sends signals with successive numbers separated by a constant value to multiple second circuits in different clock domains, with a third circuit configured to verify the integrity of these signals by comparing them with predetermined values and detecting errors through a comparison and delay mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signals are transmitted across different clock domains with different frequencies, then signal transmission between circuits is enabled, but errors occur due to bit value changes and synchronization issues
Solution Approach 1:
The patent applies preliminary action by sending test signals with known constant value separations before actual data transmission. The third circuit performs verification of the constant value separation property in advance, allowing the system to detect and correct potential synchronization issues before they affect real data. This preparatory verification ensures that the transmission path is properly synchronized when actual data flows through the system.
Solution Approach 2:
The patent implements feedback by using the verification results from the third circuit to adjust and control the transmission process. When the constant value separation is verified as correct, the system confirms proper synchronization. If verification fails, the system can detect errors and take corrective actions. This feedback mechanism ensures continuous monitoring and maintenance of signal integrity across clock domain boundaries.
2Reliability
If verification circuits are added to detect errors across clock domains, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by placing verification functionality specifically at the receiving end (third circuit) where signals enter different clock domains, rather than adding verification throughout the entire system. The verification is localized to the critical interface points between clock domains. This approach provides necessary error detection only where clock domain transitions occur, avoiding unnecessary complexity in other parts of the system.
Solution Approach 2:
The patent uses copying by creating simplified test versions of data signals with known constant value separations. These test signals are copies designed specifically for verification purposes, allowing the system to check transmission integrity without requiring complex verification logic for every possible data pattern. The copying principle enables efficient verification using representative test cases rather than exhaustive checking.
Data Source
AI summary
In an embodiment a device includes a first circuit configured to send a signal comprising numbers successively separated by a constant value to at least one second circuit, each second circuit being in a clock domain different from a clock domain of the first circuit and at least one third circuit configured to determine whether the successive numbers of the signal received by the second circuit are separated by the constant value, wherein the signal is sent to a respective third circuit in each of the clock domains different from the clock domain of the first circuit.