Memory Controller Test Circuitry for 3D-IC Timing Measurement
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Solution Overview
Problem
Integrated circuit (IC) devices in directly attached configurations, such as 3D-ICs, pose challenges in testing input and output timing parameters due to inaccessible pins, making it difficult to ensure proper operation, especially when directly attached to another IC device.
Innovation Solution
Incorporating an internal test signal generator and test signal wires that allow for precise adjustment of clock and data signals, enabling the measurement of timing parameters like setup and hold times without impacting global clock signals, thereby isolating and testing individual IC dies within the bonded structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If IC devices are directly attached in 3D-IC configuration, then integration density and compactness are improved, but accessibility of pins for testing deteriorates
Solution Approach 1:
The patent introduces an intermediary testing mechanism where test signals are injected into internal nodes of the IC device through existing functional interfaces. This mediator approach allows external test equipment to access internal timing parameters without physically accessing the inaccessible pins, thus resolving the contradiction between compact integration and test accessibility.
Solution Approach 2:
The IC device performs self-testing by utilizing its own functional interfaces to inject test signals and measure timing parameters. The device's internal circuitry serves itself for testing purposes, eliminating the need for external physical access to pins while maintaining the ability to measure critical timing parameters like setup and hold times.
2Measurement precision
If test equipment accesses input and output pins directly, then measurement capability is improved, but device configuration flexibility deteriorates
Solution Approach 1:
The patent makes the functional interfaces serve dual purposes: normal operational data transfer and timing parameter testing. By injecting test signals through the same interfaces used for data communication, the system achieves precise timing measurements without requiring separate dedicated test pins, thus maintaining device configuration flexibility while enabling accurate measurement.
3Measurement precision
If global clock signals are used for testing, then timing reference accuracy is improved, but signal interference deteriorates
Solution Approach 1:
The patent segments the timing reference function by creating dedicated test clock signal paths separate from the global operational clock signals. Test-specific clock signals are generated and routed independently to avoid interference with normal device operation, allowing accurate timing measurements without causing signal interference to the global clock distribution network.
Data Source
AI summary
A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.