PLL Test Circuit Using Single-Pattern Multi-Frequency Verification
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Solution Overview
Problem
Existing phase locked loop (PLL) systems require multiple test patterns to verify device under test (DUT) functions at different output frequencies, leading to inefficiencies in time and effort for testing.
Innovation Solution
A circuit comprising a digital converter, evaluation circuit, and duty correction circuit that adjusts the first frequency and duty cycle of input signals to generate output frequencies, allowing a single test pattern to verify DUT functions across a range of output frequencies by using a lookup table to determine parameter levels and adjust output signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test patterns are used to verify DUT functions at different output frequencies, then testing coverage is improved, but testing time and complexity increase
Solution Approach 1:
The patent implements a universal test pattern that can verify DUT functions across multiple output frequencies (312.5 MHz to 3500 MHz) through a single test configuration. The frequency multiplication mechanism allows one test pattern to effectively test multiple frequency points, eliminating the need for separate test patterns for each frequency and thereby reducing testing time while maintaining comprehensive coverage.
Solution Approach 2:
The patent changes the output frequency parameter dynamically through frequency multiplication (N=2, 4, 8, 16) while keeping the test pattern structure constant. By varying the multiplication factor N, the system can generate different output frequencies from a single input frequency, allowing comprehensive functional verification across the frequency range without requiring multiple distinct test patterns.
2Reliability
If multiple test patterns are used to verify DUT functions at different output frequencies, then testing accuracy is improved, but device complexity increases
Solution Approach 1:
The test system incorporates a universal test pattern design that can adapt to multiple output frequencies through frequency multiplication. This single multi-functional test pattern reduces the overall number of test patterns needed, thereby simplifying the testing system architecture while maintaining the ability to accurately verify DUT functions across the full frequency range.
Solution Approach 2:
The patent introduces a frequency multiplication mechanism as an intermediary between the input signal and the DUT. This intermediary component (with multiplication factors N=2, 4, 8, 16) enables a single test pattern to effectively generate multiple output frequencies, reducing the complexity of having multiple separate test patterns while preserving testing accuracy through controlled frequency variation.
3Productivity
If frequency multiplication is implemented to generate multiple output frequencies, then testing efficiency is improved, but circuit complexity increases
Solution Approach 1:
The patent implements frequency multiplication by changing the parameter N (multiplication factor) to generate different output frequencies (312.5 MHz to 3500 MHz). This parameter-based approach allows efficient frequency variation without requiring completely separate circuit paths for each frequency, thereby improving testing efficiency while keeping the circuit structure relatively simple and reusable across different frequency points.
Data Source
AI summary
A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.