ADC Built-In Self-Test Using a Reduced-Range Test Array

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Solution Overview

Problem

Existing analog-to-digital converters (ADCs) face challenges in efficient self-testing due to the need for test arrays that match the full measurement range of main arrays, leading to increased complexity, cost, and potential inaccuracies, especially for higher bit counts.

Innovation Solution

The implementation of a test array with a smaller measurement range that can selectively test portions of the main array using a processing circuitry to run conversion algorithms, allowing for reduced chip space and improved accuracy by using a test array with finer resolution to cover partial measurement ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a test array matches the full measurement range of the main array, then complete coverage of all circuit elements is achieved, but the complexity, cost, and chip space increase significantly

Engineering Contradiction:
Improvetesting completenessVSAvoidtest array complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the main array testing into multiple segments by using different start values. Instead of testing all elements simultaneously with one large test array, the system segments the measurement range and tests different portions sequentially, reducing the required test array size and complexity for each test segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by testing only a portion of the main array elements in each test operation. By adjusting the start value, the test array tests a subset of elements rather than the complete array in one go, allowing the test array to be smaller while still achieving comprehensive coverage through multiple test passes.

Inventive Principle:
Principle #16Partial or excessive action

2Measurement precision

If a test array covers the full measurement range, then all parameter values are tested, but the resolution and accuracy for individual elements decrease

Engineering Contradiction:
Improveparameter value accuracyVSAvoidtest array size
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent applies local quality by concentrating the test array's measurement capability on a specific portion of the main array at a time. By adjusting the start value to target specific segments, the test array achieves high resolution and accuracy for those local portions, rather than diluting its precision across the entire measurement range simultaneously.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If level-shifting techniques are used to expand test array range, then full main array coverage is achieved, but manufacturing complexity and potential inaccuracies increase

Engineering Contradiction:
Improvemeasurement range coverageVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Instead of physically modifying the test array through level-shifting techniques, the patent changes the operational parameters by adjusting the start value in the conversion algorithm. This software-based parameter change allows the same fixed test array to effectively cover different portions of the main array, avoiding the manufacturing complexity of variable-range hardware circuits.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10761135B2Built-in self test for an array of circuit elements
Publication Date: 2020.09.01 INFINEON TECHNOLOGIES AG
  • US10761135B2 patent drawing
  • US10761135B2 patent drawing
  • US10761135B2 patent drawing

AI summary

In some examples, a device includes a main array of circuit elements representing a main measurement range of parameter values and a test array of circuit elements representing a test measurement range of parameter values, the test measurement range being less than the main measurement range. The device also includes processing circuitry configured to select a portion of the main array of circuit elements representing a partial measurement range, the partial measurement range being less than or equal to the test measurement range. The processing circuitry is also configured to test the portion of the main array of circuit elements using the test array of circuit elements.