Analogue/Digital Conversion TRIZ Cases

Charge balancing with asynchronous and fractional counting improves gas sensor accuracy across wide resistance ranges while reducing drift error.

A clocked digital delay and latch let a time-encoding modulator cut circuit complexity, power use, and quantization noise.

Dynamic current control keeps comparator response fast during comparison while cutting A/D conversion power in other periods.

Real-time DAC clock modulation adds jitter and timing impairments to test signals, expanding baud rate coverage for DUT margin testing.

Multiple current and voltage sampling stages boost line receiver bandwidth while preserving linearity at lower supply voltage.

Parallel offset compensation and staged sampling reduce kickback noise, enabling faster, lower-voltage DQ data sampling.

Dummy-load charge compensation keeps reference draw constant in double-sampled delta-sigma converters, reducing crosstalk and non-linearity.

A delay line and decoder boost edge timing resolution without raising clock frequency, cutting power use and noise emission.

Time-division gamma voltage groups cut display data driver line count, area, and power while preserving accurate channel voltage selection.

N-fold temporal multiplexing improves particle flux measurement by reducing ADC jitter and gain errors while raising temporal resolution and SNR.

A charge-pump SAR TDC retains residual charge to improve PLL resolution, bandwidth, and noise performance with lower power.

Negative phase stepping and barrel-shifting retimers synchronize TI clock layers for higher throughput with lower area and power.

A square-wave and DC excitation scheme measures feedback DAC source-cell mismatch under the same bias condition, improving linearity and THD.

A split P-type and N-type driver with level shifting pushes clock swing beyond core supply rails to improve speed and dynamic range.

Charge-storing elements restore sampling charge to cancel differential and common-mode input currents while cutting noise, area, and power.

By encoding bits through transition presence and phase shifts, this case cuts signal transitions and dynamic power while preserving data rate.

Periodic swapping between sine and cosine signal paths exposes gain, offset, and phase mismatches and enables fast compensation.

Embedded truncation and segmentation use internal DAC feedback to cut CTDSM noise without added latency or extra combiners.

A dual-mode ADC measures DAC unit capacitance ratios internally to correct mismatch errors without adding significant circuit hardware.

Level-based frequency attenuation cuts quantization noise while preserving audible sound components for better audio quality.

Serial HFP-then-PBAP Bluetooth linking stabilizes call history transfer in in-vehicle handsfree systems while keeping software handling simpler.

Input-signal edges replace external timing in successive-approximation time-to-digital conversion, cutting power use and control complexity.

Dynamically trimmable capacitors compensate temperature drift in a delta-sigma ADC reference, keeping output accurate after single-point calibration.

Adaptive quantization across signal subranges cuts ADC error and extends dynamic range for image sensing under varying light conditions.

Bootstrap-signal autocorrelation improves receiver sampling frequency offset estimation under low SNR and wide pilot intervals.

A 2nd-order-hold interpolation filter and I/Q-interleaving RF-DAC suppress sampling replicas and LO harmonics in compact RF transmitters.

Recursive subset voltage comparison estimates DC level ranges with fewer comparators, lower power use, and simpler calibration.

A DPDT multiplexer precharges to a reference voltage before ECG channel selection, cutting switching artifacts and speeding ADC settling.

Charge-storing elements offset sampling current at the input node, cutting buffer-amplifier noise, power use, and circuit area.

R-2R RDAC and IDAC trimming replaces binary-weighted resistors, shrinking op-amp offset trim circuits while driving offset near zero.

Capacitor terminal switching extends current integrator dynamic range without discharge, preserving sensitivity, low noise, and temporal coherence.

A switch-capacitor front end accumulates touch-signal deviation before cyclic ADC conversion to cut noise, EMI, power use, and circuit area.

Input shuffling reroutes signals around defective cross-points in crossbar arrays to preserve computing accuracy without redundancy or retraining.

Interpolating between nearby temperature trim codes enables precise voltage control with lower circuit resource use across varying temperatures.

A dual-difference amplifier buffer enforces a stable differential reference and rejects common-mode noise during ADC conversion.

A hybrid current injector and tapered DAC linearize differential clock duty cycle correction while reducing parasitic capacitance and power.

Hadamard-based averaging lets grid digitizer channels be sampled simultaneously to improve resolution and dynamic range with lower ADC power.

Variable quantizer analog gain offsets speaker driver voltage modes to keep combined gain stable and calibrate non-ideal characteristics.

Switches tie comparator internal nodes to equal potentials before operation, canceling differential kickback noise and improving ADC SNR.

Clock-synchronized feedback with a digital delay and latch simplifies TEM circuitry while preserving signal accuracy and lowering power.

Breaking the feedback path and holding the output lets a current sense amplifier settle faster with less noise amplification in battery sensing.

Capacitor-defined gain amplifier cells cut OLED sensing inter-channel errors while resisting parasitic capacitance and offset drift.

A smaller test array checks selected ADC array segments, cutting chip area and complexity while improving self-test accuracy.

Hybrid current injection and a tapered DAC linearize duty cycle correction steps, avoid sub-threshold operation, and cut parasitic capacitance.

A parallel sub-sampled ADC path monitors the SerDes eye in real time, cutting area and power without degrading the main signal.

A feedback time register and digital-to-time loop shape quantization noise for 1-2 ps resolution with low power and PVT robustness.

A coupling stage with NMOS and cascode transistors raises single-stage differential op-amp gain while keeping common-mode output controlled.

Multiple interpolation cells keep current consumption constant to cut dynamic errors, INL, and power loss in digital-to-time conversion.

Doubling RFDAC sampling to 2fc suppresses baseband replicas and LO remodulation noise while improving EVM, ACLR, and quantization noise-floor.

Multiple digital loop filters, butterfly mixers, and adaptable ADC feedback cut THD and latency in audio amplifier control.