Multi-Bit ADC with Embedded Noise Shaping for Low-Latency ELD Compensation
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Solution Overview
Problem
High-speed continuous-time delta-sigma modulators face challenges in maintaining excess loop delay (ELD) timing margins due to the introduction of extra digital circuits for noise reduction, which increases latency and hardware complexity, making them unsuitable for applications with stringent timing requirements.
Innovation Solution
Implementing a multi-bit analog-to-digital converter (ADC) with embedded noise-shaped truncation, segmentation, and ELD compensation techniques, which allow for reduced hardware complexity and latency by performing error feedback summing in the analog domain, using internal DACs to manage noise shaping and truncation residues without additional combiners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extra digital circuits are added to the CTDSM for additional digital processing to reduce noise, then noise performance is improved, but latency increases and ELD timing margin is reduced
Solution Approach 1:
The patent combines multiple digital processing functions (noise shaping, truncation, segmentation, ELD compensation) into a single integrated digital circuit block within the quantizer. This merging eliminates the need for separate digital processing stages that would otherwise be required, thereby achieving improved noise performance without proportionally increasing latency.
Solution Approach 2:
The digital circuit is designed to perform multiple functions simultaneously: noise shaping, truncation, segmentation, and ELD compensation. This multi-functionality allows a single digital processing stage to achieve what would traditionally require multiple separate circuits, thus improving noise performance while minimizing the latency penalty.
2Measurement precision
If extra digital circuits are added to the CTDSM for additional digital processing, then noise performance is improved, but hardware complexity increases
Solution Approach 1:
The patent merges multiple digital processing functions into a single integrated digital circuit block, reducing the overall hardware complexity compared to implementing noise shaping, truncation, segmentation, and ELD compensation as separate digital circuits. This consolidation achieves improved noise performance while minimizing the increase in hardware complexity.
Solution Approach 2:
The digital circuit is designed to be self-sufficient by integrating all necessary processing functions (noise shaping, truncation, segmentation, ELD compensation) within a single block that operates autonomously on the quantizer output. This self-service approach eliminates the need for additional external digital processing stages, thereby improving noise performance without proportionally increasing hardware complexity.
3Device complexity
If feedback DAC resolution is reduced to simplify hardware, then hardware complexity is reduced, but noise shaping performance deteriorates
Solution Approach 1:
The patent implements feedback mechanisms within the digital circuit that compensate for the reduced resolution of the feedback DAC. By using digital signal processing techniques including noise shaping and ELD compensation, the system maintains effective noise shaping performance even with a lower-resolution feedback DAC, thus reducing hardware complexity while preserving noise shaping performance.
Solution Approach 2:
The patent changes the operating parameters of the system by using digital processing to compensate for the reduced feedback DAC resolution. Through techniques such as noise shaping and ELD compensation, the system achieves equivalent or improved noise shaping performance with a lower-resolution feedback DAC, thereby reducing hardware complexity without sacrificing noise shaping performance.
Data Source
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AI summary
An exemplary quantizer (116, 200) includes a multi-bit analog-to-digital converter, ADC, (204) and a first digital-to-analog converter, DAC, feedback circuit (210). The multi-bit ADC (204) has an internal DAC (402, 1002) associated with comparison of each sampled analog input of the multi-bit ADC (204). The multi-bit ADC (204) converts a currently-sampled analog input into a first digital output (S1). A first noise-shaped truncation output (S2) is derived from the first digital output (S1). The first DAC feedback circuit (210) transfers a first truncation residue (S3) associated with the first noise-shaped truncation output (s2) to the internal DAC (402, 1002). The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC (204) via the internal DAC (402, 1002).