Delay-Line Time Capture Circuit for High-Resolution Edge Timing
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Solution Overview
Problem
Current time capture circuits in microcontrollers for high-end applications face challenges in achieving high resolution timing control, as the required resolution exceeds the maximum allowable from the operating clock frequency, leading to increased module die size, power consumption, and noise sensitivity, with no known solution except increasing the operating clock frequency.
Innovation Solution
A high resolution time capture circuit is implemented using a delay line to generate replicas of the input signal, a free-running counter to capture counter values, and a decoder to compute capture values by shifting and comparing signal values, allowing for precise timing measurement without increasing the operating clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the operating clock frequency is increased to achieve higher timing resolution, then measurement precision is improved, but power consumption increases and noise emission increases
Solution Approach 1:
The time capture circuit is segmented into multiple functional blocks operating at different clock frequencies: a first counter block operates at the system clock frequency while a second counter block operates at a higher frequency clock signal. This segmentation allows each block to operate optimally at its required frequency without forcing the entire system to run at high frequency, thereby reducing overall power consumption while maintaining high timing resolution capability.
Solution Approach 2:
The patent introduces a temporal dimension by using delayed versions of the input signal fed to different counter blocks. The first counter receives the original input signal while the second counter receives a delayed version, allowing both counters to operate simultaneously at different frequencies and capture timing information at multiple resolution levels, achieving high precision without requiring the entire system to operate at high frequency.
2Measurement precision
If the operating clock frequency is increased to achieve higher timing resolution, then measurement precision is improved, but noise emission increases
Solution Approach 1:
The time capture circuit is segmented into multiple functional blocks operating at different clock frequencies: a first counter block operates at the system clock frequency while a second counter block operates at a higher frequency clock signal. This segmentation allows each block to operate optimally at its required frequency without forcing the entire system to run at high frequency, thereby reducing overall power consumption while maintaining high timing resolution capability.
Solution Approach 2:
The patent introduces a temporal dimension by using delayed versions of the input signal fed to different counter blocks. The first counter receives the original input signal while the second counter receives a delayed version, allowing both counters to operate simultaneously at different frequencies and capture timing information at multiple resolution levels, achieving high precision without requiring the entire system to operate at high frequency.
3Measurement precision
If the operating clock frequency is increased to achieve higher timing resolution, then measurement precision is improved, but module die size increases
Solution Approach 1:
The time capture circuit is segmented into multiple functional blocks operating at different clock frequencies: a first counter block operates at the system clock frequency while a second counter block operates at a higher frequency clock signal. This segmentation allows each block to operate optimally at its required frequency without forcing the entire system to run at high frequency, thereby reducing overall power consumption while maintaining high timing resolution capability.
Solution Approach 2:
The patent employs a universal time capture architecture that can operate at multiple clock frequencies through configurable counter blocks. The first and second counter blocks can be selectively enabled or configured based on the required timing resolution, allowing the same hardware structure to serve multiple precision requirements without requiring separate dedicated circuits for each resolution level, thus optimizing die size utilization.
Data Source
AI summary
A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.