Feedback Time-to-Digital Converter for Low-Power 1-2 ps Resolution

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Solution Overview

Problem

Current time-to-digital converters face challenges in achieving high resolution and low power consumption, particularly in low-power mobile applications, due to limitations in time resolution, noise shaping, and sensitivity to process-voltage-temperature variations.

Innovation Solution

The implementation of a feedback structure with a time register and noise-shaping characteristics to improve accuracy, utilizing oversampling and a high-order noise-shaping method that shifts quantization noise to higher frequencies, reducing in-band noise and enhancing resolution to 1-2 ps, while maintaining low power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a Vernier TDC uses two delay lines with very small delay difference to achieve high time resolution, then time resolution is improved, but the number of inverter stages increases leading to delay mismatch and increased power consumption

Engineering Contradiction:
Improvetime resolutionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements a feedback mechanism where the quantization error from the time-to-digital conversion is fed back through a digital-to-time converter and added to the original time interval measurement. This feedback loop enables noise shaping that pushes quantization noise to higher frequencies, allowing for higher effective resolution without proportionally increasing the complexity and power consumption of the delay lines.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters by using a feedback-based noise shaping approach that transforms the quantization error spectrum. Instead of directly resolving fine time differences with extremely precise delay elements, the system uses oversampling and noise shaping to achieve high resolution, effectively changing how the measurement is performed rather than relying solely on physical parameter precision.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If a Vernier TDC uses a very large number of inverter stages to cover a large detection range, then detection range is improved, but delay mismatch increases reducing measurement accuracy

Engineering Contradiction:
Improvedetection rangeVSAvoidtime resolution
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent segments the time measurement into coarse and fine components. The coarse measurement covers the large detection range using fewer delay stages, while the fine measurement resolves the residual time difference with higher precision. This segmentation allows the system to achieve both large detection range and high time resolution without requiring an excessively large number of inverter stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The feedback mechanism retrieves and reprocesses the quantization error from the coarse measurement. By feeding back the residual time difference through a digital-to-time converter and adding it to the coarse measurement, the system achieves high overall precision without needing all delay stages to operate at maximum precision, thus reducing the impact of delay mismatch.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If a gated-ring oscillator TDC operates in high frequency to achieve noise-shaping characteristic, then quantization noise is pushed to higher frequencies, but power consumption becomes very high

Engineering Contradiction:
Improvenoise-shaping performanceVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces the mechanical/high-frequency oscillating system (gated-ring oscillator) with a digital feedback-based noise shaping system. Instead of relying on high-frequency oscillation to achieve noise shaping, the system uses digital oversampling and feedback to push quantization noise to higher frequencies, achieving the same noise-shaping performance at lower power consumption.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Measurement precision

If the time-to-digital converter resolution is improved to about 1 ps, then measurement precision is improved, but device complexity increases significantly

Engineering Contradiction:
Improvetime resolutionVSAvoidconverter complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The feedback mechanism allows the system to achieve high resolution by processing quantization error rather than requiring all measurement components to operate at maximum precision simultaneously. The feedback loop enables resolution enhancement through noise shaping and error correction, reducing the need for extremely precise and complex physical components.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the approach to achieving high resolution by using digital signal processing techniques (oversampling, noise shaping, feedback) rather than relying solely on physical component precision. This parameter change from physical precision to computational precision reduces device complexity while maintaining high measurement resolution.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3502804B1Time-to-digital converter
Publication Date: 2020.07.22 HUAWEI TECH CO LTD
  • EP3502804B1 patent drawingFigure 1
  • EP3502804B1 patent drawingFigure 2
  • EP3502804B1 patent drawingFigure 3

AI summary

A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time-domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Qerr) at the first node (308, 408).