Clock-Synchronized Time-Encoding Modulator for Low-Noise Conversion
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Solution Overview
Problem
Existing signal modulators, such as sigma delta modulators and time-encoding modulators, face challenges in achieving smaller and lower power designs while maintaining accurate signal conversion, particularly in generating pulse-width modulation signals without introducing quantization noise and requiring complex circuitry for periodic reference signals.
Innovation Solution
A time-encoding modulator design incorporating a forward signal path with a comparator, filter, and digital delay element within a feedback loop, synchronized to a clock signal, which includes a latching element and a cycle period controller to control the cycle period of the time-encoded signal, allowing for reduced power consumption and compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time-encoding modulators use operational amplifier circuitry to generate periodic reference signals, then accurate signal conversion is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the operational amplifier circuitry from the modulator design. Instead of using complex op-amp based periodic reference signal generation, the invention uses a simplified digital delay element synchronized to a clock signal, removing unnecessary complexity while maintaining the essential timing function.
Solution Approach 2:
The modulator uses a self-oscillating mechanism where the feedback loop with the digital delay element automatically generates the periodic reference signal through the natural propagation delay, eliminating the need for external or dedicated reference signal generation circuitry. The system serves itself by using the inherent delay characteristics of the feedback path.
2Productivity
If sigma delta modulators use fixed frequency sampling, then digital signal conversion is achieved, but quantization noise is introduced into the signal
Solution Approach 1:
The patent implements dynamic frequency operation where the modulator's operating frequency is not fixed but varies based on the input signal characteristics. The feedback loop with digital delay creates a natural frequency modulation effect that adapts to the signal being converted, preventing the stationary quantization noise patterns that occur with fixed-frequency sampling.
3Area of stationary object
If modulators are designed for smaller size and lower power consumption, then device compactness is achieved, but signal conversion accuracy may deteriorate
Solution Approach 1:
The patent replaces traditional analog operational amplifier circuits with digital delay elements and logic circuits. This substitution allows for smaller device area since digital circuits can be more compactly implemented, while the synchronous operation to a clock signal maintains timing precision and signal conversion accuracy.
Solution Approach 2:
The invention changes the fundamental operating parameters from analog continuous-time operation to digital discrete-time operation synchronized to a clock. This parameter change enables compact implementation while maintaining accuracy through precise digital timing control, as the conversion accuracy depends on clock synchronization rather than analog component precision.
4Device complexity
If conventional modulators do not synchronize output transitions to a clock signal, then circuit simplicity is maintained, but timing precision and synchronisation capability are reduced
Solution Approach 1:
The patent uses a feedback loop that incorporates a digital delay element synchronized to a clock signal. The output of the modulator is fed back through this delay element, and the synchronized nature of the delay ensures that all output transitions occur at precise clock-aligned times, providing both timing precision and synchronisation capability.
Data Source
AI summary
This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time encoded signal (SPWM). A comparator (101) is located within a forward signal path of a feedback loop of the TEM. Also in the feedback loop are a filter (104) and a delay element (106) for applying a controlled delay. In some embodiments a latching element (101, 302; 106, 402) is located within the forward signal path to synchronise any signal transitions output from the latching element to a received first clock signal. Any signal transitions in the output (SOUT) from the modulator are thus synchronised to the first clock signal. In some embodiments the delay element (106) is a digital delay element which is synchronised to the first clock signal.