Interleaved ADC Timing Calibration Using Programmable Delay Elements
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Solution Overview
Problem
High-speed interleaved analog-to-digital converters (ADCs) face performance degradation due to phase mismatches between sub-ADCs, which are not effectively addressed by existing calibration techniques that require significant time, impose bandwidth limitations, or result in high power consumption and complexity.
Innovation Solution
The implementation of programmable delay elements within sub-ADCs to calibrate phase mismatches by adjusting sub-clock signals based on comparison of calibration codes, allowing for precise phase matching without the need for extensive calibration time or complex adaptive filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If known timing mismatch calibration techniques are used, then phase matching is improved, but calibration time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing calibration using a test signal before normal operation, establishing optimal timing offsets in advance. The calibration phase occurs separately from data acquisition, allowing comprehensive calibration without extending the actual measurement time.
Solution Approach 2:
The calibration process is implemented as a periodic action that can be executed at defined intervals or under specific conditions. The system alternates between calibration mode and normal operation mode, enabling phase matching to be refreshed periodically without continuously consuming calibration time.
2Measurement precision
If adaptive digital filters with large number of taps are used, then phase calibration is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent extracts the timing calibration function from the main data processing path and implements it as a separate, dedicated calibration mechanism. By isolating the calibration function, the system achieves precise phase matching without requiring complex adaptive filters to be continuously active during normal operation.
Solution Approach 2:
The calibration method changes the operational parameters of the system by switching between calibration mode and normal operation mode. During calibration, specific parameters such as timing offsets are adjusted based on test signal analysis, then these parameters are fixed for efficient normal operation without requiring continuous complex processing.
3Measurement precision
If known calibration techniques are used, then phase matching is improved, but input signal bandwidth is limited
Solution Approach 1:
The calibration is performed in advance using a dedicated test signal that can be specifically designed to cover the full bandwidth of interest. This preliminary calibration establishes timing offsets that are valid across the entire frequency range, allowing subsequent high-bandwidth operation without bandwidth limitations during calibration.
Data Source
AI summary
An interleaved analog-to-digital converter, ADC, includes a first and a second sub-ADC (ADC1, ADC2) and a timing control unit (TC). The first sub-ADC (ADC1) is configured to convert a first calibration signal (V1cal) into a first calibration code (CC1) depending on a first sub-clock signal (Φ1). The second sub-ADC (ADC2) includes a programmable delay element (DE2) configured to generate a calibrated second sub-clock signal (Φ2′) by shifting a phase of a second sub-clock signal (Φ2) by a delay depending on a control signal. The second sub-ADC (ADC2) is configured to convert a second calibration signal (V2cal) into a second calibration code (CC2) depending on the calibrated second sub-clock signal (Φ2′). The timing control (TC) unit generates the control signal (CS) comparing the second calibration code (CC2) to the first calibration code (CC1).