Analogue-Digital Converters TRIZ Cases

Cross-correlation with filtering and delay adjustment estimates gain and time offsets in interleaved ADCs to reduce distortion.

Split-sample phase rotation and shared post-processing cut conversion complexity, enabling faster error estimation and correction updates.

Primary-side measuring coil feedback compensates parasitic voltage drops, enabling accurate secondary voltage control without direct high-voltage sensing.

Parallel ADC and early sensing-data transmission cut touch sensing time while reducing noise and improving touch sensitivity.

Order-aware calibration measures mismatch patterns between sub-ADCs and corrects sequence-dependent spurs to improve dynamic range and SNDR.

A built-in capacitor lets the touch driver IC switch sensitivity modes, improving indirect touch detection without changing electrode layout.

One channel generates a reference voltage for another, enabling independent ADC checks and reliable error detection without extra components.

Windowed frame fitting aligns multi-gain ADC stages to preserve low-level audio fidelity while reducing distortion and noise.

Charge-memory units and PWM edge selection let this ADC keep high conversion speed and accuracy without complex time-interleaving calibration.

Variable sampling rates shift sampling points to suppress aliasing and reconstruct distorted return pulses for mm-level distance measurement.

A time-dependent resistor helps a digital step attenuator discharge abrupt charges faster while preserving noise figure in RF receivers.

FPGA threshold sampling digitizes scintillation pulses without analog comparators, improving PET accuracy while cutting power and circuit complexity.

Built-in self-test and reverse modeling detect degraded avionics acquisition modes and correct signal accuracy loss as components age.

A free-running ADC clock with phase detection and resampling removes system clock distribution, cutting noise in MRI RF coil receivers.

Pseudo-random DAC core selection spreads interleaving spurs into the noise floor while preserving high sample rates in time-interleaved converters.

Plated metal gratings on an oxidized blackened base improve reflection, grating accuracy, and manufacturing cost in photoelectric encoder scales.

Parallel sub-octave filter banks split wide input bands into narrow paths, cutting second-order intermodulation before ADC merging.

Targets only in-band spurious mismatch profiles in time-interleaved RF ADCs to improve SFDR without high-power multi-tap filters.

Hybrid thermometer-binary MSB encoding and self-calibration correct split-capacitor DAC mismatch and parasitics for higher SAR ADC accuracy.

A shared chip select and clock let one controller sample multiple ADC data streams in parallel, cutting MCU load and component cost.

Lower-resolution ADCs capture divided voltage portions and combine coarse and fine readings for precise power-supply feedback at lower cost.

Continuous analog and digital offset feedback recenters sensor output to avoid saturation and preserve measurement accuracy under disturbances.

Removing maximum and minimum correction values lets an ADC calibration circuit reject noise and improve conversion accuracy with less averaging.

Real-time mismatch detection and adaptive compensation correct timing skew in time-interleaved ADC channels, improving signal quality and SFDR.

A ring-oscillator coarse stage plus 2D Vernier fine measurement extends TDC range while preserving picosecond-level phase resolution.

Relative bit-position encoding lets each symbol carry cross-symbol information, boosting throughput through compression despite added data-structure complexity.

Weighted additive and subtractive current driving cuts sampling capacitor size and clock cycles in high-resolution ADC conversion.

Signal-derivative cross terms and Volterra coefficients cancel ADC non-linearity and interleaving mismatch before correction bias appears.

Converting RF bandpass signals to a single sideband before sampling lowers ADC speed needs and avoids overlap during multi-signal down-conversion.

Shared multiplexers and sine-cosine processing enable simultaneous AC sensor sampling, cutting circuit size and power while removing time skew.

Dual-mode ADC sampling combines wideband signal detection with low-rate phase interferometry to calculate antenna AoA with lower SWaP-C.

A second channel generates a reference voltage so multiplexed A/D inputs can verify each measuring channel independently and detect errors.

Pseudorandom comparator threshold changes and postprocessing coefficients help interleaved ADC channels keep resolution with lower amplifier power and area.

Multi-stage time-interleaved RF sampling lowers mismatch errors, latency, and power in wideband analog-to-digital conversion.

Pseudo-random DAC core selection breaks periodic interleaving, spreading mismatch spurs into the noise floor at very high sample rates.

Subtracting lower and upper spur components in frequency bins removes ADC clock jitter and improves high-frequency measurement accuracy.

A modulated reference is superimposed on the analog input so ADC readout can self-calibrate online without interrupting measurement.

Programmable sub-clock delays calibrate phase mismatch in interleaved ADCs, cutting calibration time while improving SNR and SFDR.

A dummy photodiode and ADC switching separate leakage and photon currents, improving low-light optical sensing accuracy.

Square-wave frequency mixing lets one receiver handle changing multi-subband signals with fewer channels and lower hardware overhead.

Different-amplitude shift signals dither the analog input so a low-resolution ADC can improve precision without Σ-Δ processing or costly noise circuits.

Two parallel ADC paths isolate chopping-induced offset errors through difference and demodulation, reducing ripple, bias current, and complexity.

Excluding maximum and minimum correction values helps a capacitive ADC calibrate accurately under external noise with less averaging time.

A voltage ramp and window comparator let ADC tests count samples within a threshold window, improving accuracy with less complex equipment.

Frequency-domain mismatch estimation with integrity monitoring suppresses interleaved ADC spurs while preserving high-speed signal accuracy.

Overlapping redundant bits let a coarse-fine TDC detect and correct quantizer mismatch, preserving high-resolution timing over large intervals.