Split-Capacitor SAR ADC Calibration for Linearity and Accuracy
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Solution Overview
Problem
High-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) face accuracy limitations due to device mismatch and parasitic elements, particularly in split-capacitor DACs, which compromise differential and integral non-linearity.
Innovation Solution
A split-capacitor DAC employs a combination of thermometer and binary encoding for the Most Significant Bits (MSBs) sub-DAC, along with self-calibration methods to measure capacitor elements and compute calibration values for each ADC output code, improving accuracy beyond 11-12 bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a split-capacitor DAC is used in a high-resolution SAR ADC, then the area requirement is decreased and speed is increased, but device mismatch and parasitic elements compromise accuracy
Solution Approach 1:
The MSBs sub-DAC is segmented into two separate DACs: a thermometer-encoded DAC and a binary-encoded DAC. This segmentation allows each DAC to be optimized for its specific encoding type, reducing the negative effects of device mismatch and parasitic elements while maintaining the area benefits of the split-capacitor structure.
Solution Approach 2:
The patent changes the encoding parameter of the MSBs sub-DAC from a single encoding type to a hybrid encoding scheme combining thermometer and binary encoding. This parameter change enables the system to achieve high accuracy (beyond 11-12 bits) by leveraging the advantages of both encoding methods while mitigating their individual disadvantages.
2Use of energy by moving object
If full thermometer encoding is used for MSBs sub-DAC, then switching currents are reduced and power consumption decreases, but large amount of logic is needed which limits feasibility beyond 4-5 bits
Solution Approach 1:
The MSBs sub-DAC is divided into two separate DACs with different encoding schemes. The thermometer-encoded portion handles the most significant bits with reduced switching currents, while the binary-encoded portion handles the remaining bits with simpler logic, thereby distributing the complexity and power consumption across two optimized structures.
Solution Approach 2:
Different encoding schemes are applied to different portions of the MSBs sub-DAC based on local requirements. The thermometer encoding is applied where power consumption is critical, while binary encoding is applied where logic simplicity is more important, creating a locally optimized hybrid structure.
3Measurement precision
If device mismatch and parasitic elements are present in the DAC, then differential and integral non-linearity deteriorate, but calibration methods are needed to improve accuracy
Solution Approach 1:
The system performs self-calibration by measuring each capacitor element or group of capacitor elements and using these measurement results to compute calibration values for each ADC output code. This self-service approach compensates for device mismatch and parasitic effects without requiring external calibration equipment, thereby improving accuracy despite manufacturing variations.
Solution Approach 2:
The calibration circuitry measures the actual capacitor values and uses this feedback information to compute calibration values that compensate for mismatches. This feedback mechanism allows the system to adapt to manufacturing variations and parasitic effects, improving the differential and integral linearity of the ADC.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage. The ADC includes a comparator coupled to receive the output voltage, successive-approximation-register (SAR) circuitry coupled to the comparator and providing an uncalibrated digital value corresponding to an uncalibrated digital representation of the input voltage, and calibration circuitry configured to apply one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital.