Multi-ADC Serial Sampling with Shared Clock and Chip Select
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Solution Overview
Problem
In distributed antenna systems (DASs), the increasing number of analog-to-digital converters (ADCs) required to sample communications signals consumes a significant portion of the microcontroller unit's (MCU) resources, limiting its availability for other tasks and necessitating either more expensive ADCs with increased processing capabilities or additional MCUs for sampling.
Innovation Solution
A controller unit is configured to simultaneously sample serial digital data streams from multiple ADCs using a common chip select and clock signal, allowing for efficient parallel sampling across multiple data input ports, thereby reducing the need for additional resources and potentially lower-cost components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of ADCs is increased to sample more communications signals, then the sampling capability and coverage are improved, but the resource consumption of the MCU increases significantly
Solution Approach 1:
The patent combines multiple ADC sampling operations into a single unified sampling phase. All ADCs are triggered simultaneously by a common sampling clock, and their results are collected in parallel during one MCU interrupt cycle, rather than sequentially sampling each ADC individually. This merging of operations maintains high sampling capability while significantly reducing MCU resource consumption.
Solution Approach 2:
The system performs preliminary sampling preparation by configuring all ADCs with identical sampling parameters (clock frequency, resolution, trigger source) before the sampling operation begins. The sampling clock is pre-configured to simultaneously trigger all ADCs, and the MCU interrupt handler is pre-programmed to collect results from all ADCs in a single execution cycle, eliminating the need for repeated configuration during sampling.
2Productivity
If ADCs with increased processing capabilities are used to handle multiple data streams, then the sampling efficiency is improved, but the system cost increases
Solution Approach 1:
The patent segments the sampling function into two independent parts: (1) the ADC hardware that performs parallel analog-to-digital conversion, and (2) the MCU that performs sequential result collection and processing. This segmentation allows the use of simple, low-cost ADCs without complex built-in processing capabilities, while still achieving efficient multi-channel sampling through the divided functional architecture.
Solution Approach 2:
The common sampling clock serves multiple functions simultaneously: it acts as the trigger signal for all ADCs, provides the timing reference for synchronized sampling, and defines the sampling rate for all channels. This universal clock signal eliminates the need for separate trigger mechanisms for each ADC, reducing system complexity and cost while maintaining sampling efficiency.
3Productivity
If additional MCUs are added to handle sampling tasks, then the processing capacity is improved, but the system complexity and cost increase
Solution Approach 1:
The MCU continuously monitors a single interrupt flag that indicates when all ADC conversions are complete. Once the flag is set, the MCU executes a continuous sampling routine that collects results from all ADCs, processes the data, and prepares for the next sampling cycle without interruption. This continuous action pattern allows one MCU to efficiently handle multiple ADCs without requiring additional processing units.
Data Source
AI summary
Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.