Interleaved ADC Calibration for Gain and Timing Mismatch
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) in time-interleaved architectures face challenges in controlling and compensating for gain and timing mismatches between channels, which affect their performance and throughput in high-bandwidth applications.
Innovation Solution
A system and method that includes a signal generator, parallel ADCs, filtering components, delay adjustment components, and a cross-correlating component to determine gain error and time-offset calibration data, which are used to update the output digital signal and calibrate individual ADCs for gain mismatches and timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time-interleaved architecture is used to improve ADC throughput, then productivity increases, but manufacturing precision deteriorates due to gain and timing mismatches between channels
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before normal operation to determine gain and timing error values. The system captures calibration signals, computes error values, and stores them for subsequent compensation during regular ADC operation, preventing mismatch issues from affecting throughput.
Solution Approach 2:
The patent implements feedback by using the computed gain and timing error values to compensate the ADC channel outputs. The calibration system continuously monitors and adjusts for mismatches by applying correction factors to each channel, ensuring that the time-interleaved architecture maintains both high throughput and precision.
2Productivity
If multiple parallel ADCs are used to increase bandwidth, then productivity increases, but device complexity increases due to multiple calibration components
Solution Approach 1:
The patent applies universality by designing a calibration system that handles both gain and timing error compensation using a unified approach. The same calibration infrastructure (signal generator, capturer, processor) serves multiple calibration functions across all ADC channels, reducing overall system complexity despite the presence of multiple parallel converters.
Solution Approach 2:
The patent implements self-service by enabling the calibration system to automatically characterize and compensate for its own mismatches. The ADCs calibrate themselves by capturing calibration signals, computing their own error values, and applying corrections without requiring external intervention, thereby simplifying the overall calibration architecture.
Data Source
AI summary
Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a set of filtering components configured to at least filter image components and cause a phase shift in the output signals. One or more delay adjustment components can cause a delay to at least the output of the parallel ADCs and the set of filtering components. A cross-correlating component can be utilized to cross-correlate the output of the parallel ADCs with an output signal of at least one filtering component of the set of filtering components and an output signal of at least one delay adjustment component of the set of delay adjustment components. A conversion component determines polar coordinates from rectangular coordinates from the output of the cross-correlating component. Thereafter, a time-offset and gain estimator component can determine one of gain error calibration data or time-offset calibration data based at least in part on an output signal of the conversion component, which can be stored and/or used to calibrate individual time-interleaved ADCs.