Current-Steering ADC Comparator Architecture for Fast High Resolution
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Solution Overview
Problem
Current analog-to-digital converters face challenges in achieving high resolution and fast conversion rates while minimizing the size of sampling capacitors and reducing clock cycles, particularly in current steering techniques.
Innovation Solution
The proposed solution involves a current steering analog-to-digital converter design that includes a current driving circuit with additive and subtractive current driving mechanisms, a comparison circuit with multiple comparators, and a decoder to generate binary output data, which adjusts voltage levels using weighted currents and reference voltages to optimize the conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current steering technique is used to achieve high resolution and fast conversion rates, then conversion speed and resolution are improved, but sampling capacitor size increases and clock cycles increase
Solution Approach 1:
The patent divides the comparison process into multiple stages using a multi-bit flash ADC structure, where comparators are segmented into groups that process different bit ranges. This segmentation allows the system to achieve high conversion speed by processing multiple bits simultaneously while using smaller sampling capacitors compared to a single-stage high-resolution ADC.
Solution Approach 2:
The patent introduces an additional dimension of processing by implementing a two-stage conversion architecture: first stage uses flash ADC for coarse conversion of MSBs, and second stage handles LSBs. This dimensional approach to problem-solving allows achieving high resolution without proportionally increasing capacitor size, as each stage operates with optimized capacitor values for its specific resolution requirement.
2Measurement precision
If current steering technique with high performance current sources and switches is used, then conversion resolution is improved, but device complexity increases
Solution Approach 1:
The current steering DAC is segmented into multiple current source groups corresponding to different bit weights (MSB and LSB groups). Each group uses switches and current sources optimized for its specific resolution requirement, reducing the overall complexity compared to a single high-resolution current steering stage that would require exponentially more complex current sources and switches.
Solution Approach 2:
Different parts of the current steering network use different current source precision levels matched to their bit significance. MSB current sources require higher precision but fewer units, while LSB current sources use lower precision but more units. This local quality differentiation optimizes the trade-off between resolution and complexity by allocating resources according to actual needs at each bit position.
3Measurement precision
If multiple comparators are used to achieve high resolution conversion, then conversion resolution is improved, but clock cycles increase
Solution Approach 1:
The patent segments the comparator array into multiple flash ADC stages that operate in parallel for coarse conversion, followed by a second stage for fine conversion. This segmentation enables high-resolution conversion to be achieved in fewer clock cycles because the first stage rapidly determines MSBs in a single flash comparison, reducing the total conversion time compared to sequential comparison methods.
Solution Approach 2:
The first flash ADC stage performs preliminary action by quickly determining the most significant bits of the conversion result before the second stage processes the least significant bits. This preliminary determination of MSBs allows the system to narrow down the voltage range early, reducing the number of subsequent comparison steps needed and thereby minimizing total clock cycles while maintaining high resolution.
Data Source
AI summary
An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.