Multi-Layer Time-Interleaved ADC for Wideband RF Sampling

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Solution Overview

Problem

Conventional analog-to-digital conversion processes in communications are complex, time-consuming, and power-intensive, often introducing errors or distortions, especially when handling very wideband signals.

Innovation Solution

A multi-layer time-interleaved analog-to-digital converter (ADC) system that samples RF signals in multiple stages with reduced sampling rates, using a single-chip architecture to integrate RF front-end, baseband, and digital signal processing, thereby reducing clocking and sampling mismatch errors and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional analog-to-digital conversion is used, then conversion functionality is provided, but the process is complex, time-consuming, and power-intensive

Engineering Contradiction:
Improveconversion speedVSAvoidconversion complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the analog-to-digital conversion process into multiple parallel sub-converters, each handling a portion of the input signal spectrum. This segmentation allows simultaneous processing of different frequency bands, improving overall conversion speed while distributing complexity across multiple simpler units rather than one complex converter

Inventive Principle:
Principle #1Segmentation

2Productivity

If conventional analog-to-digital conversion is used, then conversion functionality is provided, but considerable power is required

Engineering Contradiction:
Improveconversion efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

By segmenting the conversion task across multiple parallel sub-converters operating at lower individual power levels, the system achieves high overall productivity without requiring one high-power converter. The distributed architecture reduces peak power consumption and improves energy efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs time-interleaved sampling where multiple sub-converters operate in periodic alternation, each processing specific time intervals or frequency bands. This periodic operation allows efficient utilization of converter resources and reduces average power consumption compared to continuous operation of a single high-speed converter

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If conventional analog-to-digital conversion is used, then conversion is performed, but errors or distortion are introduced

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the wideband input signal into multiple narrower frequency bands, each processed by a dedicated sub-converter. This segmentation reduces the complexity requirements for each individual converter while maintaining high overall accuracy, as each sub-converter operates within its optimized frequency range with reduced distortion

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system incorporates digital signal processing that combines outputs from multiple sub-converters with correction mechanisms. This feedback-based reconstruction process compensates for individual sub-converter errors and distortion, improving overall measurement precision while managing complexity through systematic error correction

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9985777B2Multi-layer time-interleaved analog-to-digital convertor (ADC)
Publication Date: 2018.05.29 ENTROPIC COMM INC
  • US9985777B2 patent drawing
  • US9985777B2 patent drawing
  • US9985777B2 patent drawing

AI summary

A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.