RF ADC Interleaving Calibration for In-Band Mismatch Correction
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges in correcting frequency-dependent mismatches between parallel ADCs, leading to spurious signals that degrade the spurious-free dynamic range (SFDR), and conventional solutions require high power consumption due to multi-tap filter structures.
Innovation Solution
An interleaving calibration circuit that estimates frequency domain mismatch profiles and rejects spurious signals outside the frequency bands of interest, using a frequency-independent correction model to generate filter coefficients for correcting mismatches while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-tap filter structures are used to correct frequency-dependent mismatches, then the correction accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent extracts and rejects out-of-band spurious signals from the correction process, keeping only in-band mismatch profiles for parameter estimation. This selective extraction reduces the amount of data processed by the correction algorithm, thereby reducing power consumption while maintaining correction accuracy for signals within the frequency band of interest.
Solution Approach 2:
The patent applies local quality by focusing correction resources on frequency bands of interest rather than uniformly processing all frequencies. By identifying and prioritizing in-band mismatch profiles, the system allocates computational power selectively to where it is most needed, improving power efficiency without sacrificing correction accuracy for relevant signals.
2Reliability
If conventional mismatch correction methods are applied across all frequencies, then comprehensive correction is achieved, but computational resources are wasted on out-of-band signals
Solution Approach 1:
The system extracts only the relevant in-band mismatch profiles from the complete frequency spectrum, separating useful information from unnecessary data. This extraction process reduces computational complexity by eliminating out-of-band signals that do not contribute to the correction of signals within the frequency band of interest.
Solution Approach 2:
The patent applies partial action by performing mismatch correction only for frequency bands of interest rather than across the entire frequency spectrum. This selective approach maintains sufficient correction coverage for relevant signals while reducing overall computational complexity by omitting processing of out-of-band frequencies.
Data Source
AI summary
An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.