ADC Test Data Compression for Fewer Pins and Faster Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Testing of electronic circuits, particularly analog-to-digital converters (ADCs) with many data bits, is inefficient due to the need for direct access and serial conversion, which increases test time and costs, and requires a large number of pins and automated test equipment.
Innovation Solution
Implementing a data compression procedure that shifts out the difference between consecutive samples, using N flip-flops to latch and subtract samples, reducing the output to three bits, which can be mapped onto fewer pins, and utilizing a finite state machine to manage errors and serial output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial conversion is used to output ADC data, then the number of IC pins is reduced, but test time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-computing the difference between consecutive ADC samples and latching this difference value before output. Instead of serially converting and then processing the data, the system prepares the differential data in advance using flip-flops to store previous sample values and subtraction logic to compute differences, enabling faster parallel output of compressed test data.
2Measurement precision
If direct access to ADC with many data bits is implemented, then measurement accuracy is maintained, but the number of ATE and IC pins required increases
Solution Approach 1:
The patent extracts only the essential information needed for ADC testing by computing the difference between consecutive samples. Instead of outputting all N bits of each ADC sample, the system extracts the change value which typically requires far fewer bits to represent, thereby reducing the number of pins and ATE resources while maintaining the ability to detect ADC linearity errors.
Solution Approach 2:
The patent changes the parameter representation by transforming the ADC output from absolute sample values to differential values (changes between consecutive samples). This parameter transformation reduces the bit width required for representation while preserving the information needed to detect INL and DNL errors, thus reducing device complexity without sacrificing measurement precision.
3Device complexity
If serial conversion of ADC output data is used, then device complexity is reduced, but productivity decreases due to increased test time
Solution Approach 1:
The patent applies preliminary action by pre-computing the difference between consecutive ADC samples and latching this difference value before output. Instead of serially converting and then processing the data, the system prepares the differential data in advance using flip-flops to store previous sample values and subtraction logic to compute differences, enabling faster parallel output of compressed test data.
Data Source
AI summary
A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.