Digital Circuit Testing TRIZ Cases

Separate clock generators and a conversion circuit deliver stable variable-frequency clocks for high-speed memory DUT testing beyond tester limits.

Custom on-chip DFT adds insertion, extraction, and hybrid test circuits to improve internal node observability, fault coverage, and yield.

On-die temperature sensing and lookup-table voltage updates correct AVS sensor errors, cutting conservative margins and leakage power.

Pulse counts from two output signals are compared across time intervals to detect pin connection errors without redundant pins.

Successive numbers with a fixed step let receiving circuits detect corruption across different clock domains and preserve signal integrity.

Recording capture pulse counts and regenerating them from a reference clock improves IC at-speed fault coverage without large frequency-specific storage.

Delayed data samples and clock comparisons expose reflections, noise, and crosstalk at high-speed chip-to-chip interfaces with low power and area.

Serializer shift registers capture signal arrival before slow clock sampling, cutting FPGA timing ambiguity from about 10 ns to sub-nanosecond precision.

By comparing measurements at different loop bandwidths, the controller tunes clock recovery to reject deterministic components while tracking random jitter.

Dual clock-synchronized detection circuits compare voltage transitions to catch fault injection failures and improve semiconductor security.

Built-in test logic verifies combined reset-request propagation and connectivity, helping processing systems enter a safe state.

A tunable loopback path lets an LVDS receiver be tested across the full common-mode voltage range, improving defect detection.

Programmable ring oscillators and delay paths measure on-chip propagation delay variance without extensive test structures or off-chip circuits.

Current clamp circuits slow output current transitions before amplifier switching, reducing glitches and false failure indications in test systems.

Separate rising- and falling-edge latch paths let gated clocks toggle on every transition, cutting DET flip-flop latency and data misses.

Error-tolerant feedback narrows the circuit parameter search range despite A/D conversion errors, cutting adjustment time and improving target convergence.

Internal test signal generators shift clock and data timing to measure setup, hold, and clock-to-Q delays when bonded IC pins are inaccessible.

Clock pulse generation and output counting enable at-speed delay circuit testing, exposing defective delay cells before IC packaging.

A synchronized transmitter, receiver, and reference clock setup speeds eye-diagram measurement of DUT signal distortion without multi-equipment testing.

Slack monitors and PVT feedback adjust body bias or supply voltage by region to balance timing margin, performance, and power.

An on-chip comparator decodes merged expected-result and mask signals to ease scan-out bottlenecks, cutting chip test time and pin use.

Phased latch paths gate both clock edges for dual-edge flip-flops, cutting power and latency without missing data transitions.

Majority evaluation of adjacent TDC bits suppresses bubble transitions, improving phase error accuracy and circuit stability.

Configuring test logic during reset avoids missed early measurement windows and improves subsystem test timing after reset release.

Measured-data lookup tables tune macro model parameters across voltage and temperature conditions, improving IC simulation accuracy without long runtimes.

A built-in self-test circuit compares DAC input and output in real time to flag abnormalities and improve semiconductor reliability.

Correlated sine and cosine cancellation isolates target PLL spurs, enabling accurate tone measurement for screening and process control.

Programmable oscillators and delay paths measure on-chip propagation delay, reducing test structure area while capturing timing variation.

Parity verification across level-shifted analog and digital paths helps detect memory and transmission faults in automotive power devices.

Real-time frequency tracking and NCO mixing stabilize drifting high-frequency signals, enabling narrower-band, lower-noise power measurement.

Delayed clock and reference edge comparison with tunable thresholds enables faster, more accurate jitter detection for stable signals and data integrity.

A tunable counter switches detection thresholds to catch missing or unstable clocks faster while reducing prolonged failure signals.

On-chip decoding of merged expected-result and mask signals avoids slow scan-out comparison, reducing chip test time and pin count.

Differential compression of consecutive ADC samples cuts output pins and test time while preserving accurate circuit test data.

A marker-triggered link aligns the pulse generator with analyzer timing to remove phase ambiguity and enable absolute phase calibration.

Keeps MBFF data-out nodes at a fixed level during test mode, cutting scan-induced switching and downstream combinational power.

A split master-slave latch scheme with mode-specific clocks lowers scan-chain test power in memory without disrupting functional operation.

A sample-and-hold stage converts clock timing jitter into digital data, helping engineers verify signal quality margins in integrated systems.

Multiple FIR sub-filters are selectively connected to handle high data parallelism without longer filter lengths or excess hardware.

By generating an intermediate sampled signal before target clock edges, this circuit preserves phase detection accuracy even when high-frequency pulses are filtered.

Digital delay control measures duty cycle in GHz periodic signals without analog converters, reducing distortion, cost, and circuit area.

On-board analysis of MTJ stimulus and response waveforms cuts handshaking delays, memory load, and test decision time.

A stimulus-response controller with configurable onboard analysis cuts handshaking delays in high-speed MTJ electrical testing.

Unified ICG and control cells enable internal clock control for ATPG and LBIST, cutting dedicated pin use in low-power scan chains.

Calibration circuitry compensates input offset voltage and signal delay in signal-comparison paths, improving DC node testing accuracy and reliability.

Shift-register synchronization aligns scan enable with leaked clock pulses, enabling 2 GHz transition fault testing with fewer wait cycles.

Internal test signals delay clock and data paths to measure setup and hold times in directly attached 3D-IC dies with inaccessible pins.

A cascaded MASH delta-sigma TDC measures PLL phase noise on chip, avoiding unstable high-frequency BIST clocks and external probes.

Counts PAM4 symbol level frequencies and displays their ratios to guide Vth1-Vth3 adjustment for accurate high-speed decoding.

Duplicate adjustment data is compared in an RTC module to flag abnormalities and preserve reliable timing data during frequency correction.