Clock-Gating Cell Control for LBIST in Low-Power Scan Chains
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Solution Overview
Problem
Traditional methods for controlling clock-gating cells in low power VLSI chip designs are inadequate for implementing Logic Built-In-Self-Test (LBIST) as they require external control signals, which is not scalable and limits the availability of pins, making it difficult to achieve efficient testing.
Innovation Solution
A unified approach that integrates core logic circuits with integrated clock-gating (ICG) cells and control cells (ICCs) to provide full control over clock signals during scan-shift and scan-capture, allowing for both automated test pattern generation (ATPG) and LBIST, while eliminating the need for dedicated pins and enhancing hierarchical design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ATE control method using dedicated chip input pin is used, then clock-gating cells can be controlled for scan-shifting and capture, but pin availability is reduced and LBIST cannot be implemented
Solution Approach 1:
The patent merges the control of multiple clock-gating cells into a unified control structure where a single control signal can simultaneously control multiple ICG cells through scan chain integration. This eliminates the need for dedicated control pins for each ICG cell while maintaining full testing capability through the integrated scan chain approach.
Solution Approach 2:
The scan chain is designed to serve multiple functions: it controls clock-gating cells during scan-shifting, enables capture operations, and supports LBIST functionality. This multi-functional approach allows the same control mechanism to serve both ATE and LBIST testing methods without requiring separate dedicated pins.
2Ease of operation
If traditional approach with dedicated control pin is used, then clock control is achievable for scan operations, but LBIST cannot be implemented as all control signals must be generated inside the chip
Solution Approach 1:
The system enables self-service control where the scan chain automatically controls the clock-gating cells during LBIST operations. The control signals are generated internally within the chip through the scan chain mechanism, eliminating the need for external control pins while maintaining full automation capability for both scan operations and LBIST.
3Device complexity
If multiple dedicated pins are used to control individual clock-gating cells, then precise control is achieved, but device complexity and pin count increase
Solution Approach 1:
The patent segments the control approach by integrating ICG cell control into the scan chain structure rather than using separate dedicated pins. Each ICG cell is associated with specific scan chain elements, allowing precise control through the segmented scan chain paths while reducing overall pin count and control structure complexity.
Data Source
AI summary
An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.