Clock Signal Jitter Measurement Using Sample-and-Hold Timing
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Solution Overview
Problem
Clock signals in electronic systems, particularly in automotive and radar systems, experience signal deterioration due to jitter, which can lead to bit error rates and quality issues in high-speed communication interfaces, making it difficult to maintain predefined error margins during system integration and mass production.
Innovation Solution
A device and method utilizing a sample and hold circuit with a switching device driven by a control signal and capacitance to transform and measure clock-based signals, converting them into digital output signals that indicate jitter, allowing for assessment of clock signal quality and potential triggering of alarms or redesigns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock signal is conveyed through system integration, then the clock signal can be distributed to multiple components, but the signal quality deteriorates due to jitter
Solution Approach 1:
The patent replaces direct electrical clock signal distribution with a time measurement and comparison system. Instead of relying on the clock signal to directly control components across the system, the invention measures the clock signal's time characteristics using an ADC and compares it against reference values, substituting the mechanical/electrical signal propagation with a measurement and evaluation system that can detect and account for jitter without being corrupted by it.
Solution Approach 2:
The patent introduces an intermediary measurement system between the clock source and the components that use it. The ADC, sample stage, and evaluation logic act as intermediaries that measure the clock signal's time characteristics and provide corrected or compensated timing information to downstream components, preventing jitter from directly affecting system operation.
2Device complexity
If the clock signal is measured directly, then the measurement process is simple, but the measurement precision is insufficient to detect jitter within predefined margins
Solution Approach 1:
The patent applies preliminary action by using a sample stage to capture and hold the clock signal at specific time points before conversion. The sample stage pre-processes the signal by selecting discrete sampling moments, which prepares the signal for accurate ADC conversion and enables precise time interval measurement that can detect jitter within predefined margins.
Solution Approach 2:
The patent transitions from direct time measurement to voltage measurement of time intervals. By converting the time-based clock signal characteristics into voltage signals through the ADC, the system measures time in a different dimension (voltage domain), enabling higher precision measurement of jitter that cannot be achieved through direct time domain measurement.
3Measurement precision
If the capacitance in the sample stage is increased to improve sampling accuracy, then the sampling precision improves, but the device complexity and component requirements increase
Solution Approach 1:
The patent changes the operating parameters of the sample stage by optimizing the capacitance value to a specific range (1 pF to 100 pF) and adjusting the switching device characteristics accordingly. This parameter optimization achieves high sampling accuracy without requiring excessively large capacitance values, maintaining device complexity at acceptable levels while improving measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the monitoring and evaluation of clock signal quality within systems, ensuring compliance with quality requirements and potentially reducing BOM costs by identifying and addressing jitter issues, thereby improving system performance and reliability.
Implementation Method 1
The capacitance of the sample stage is used for accumulating charge during the time the switching device is closed
Data Source
AI summary
A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.