Dual-Edge Clock Gating Circuit for Low-Latency DET Flip-Flops
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Solution Overview
Problem
Existing clock gating techniques are inadequate for dual-edge-triggered (DET) flip-flops, as they fail to provide timely gated clock signals on both rising and falling edges, leading to latency and data misses.
Innovation Solution
A clock gating system comprising multiple logic circuits and latch circuits is designed to generate a gated clock signal that toggles with every state transition of an input clock signal, ensuring proper operation of dual-edge-triggered data storage circuits without latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating circuits are used with positive-edge-triggered flip-flops, then power consumption is reduced, but timing accuracy deteriorates on falling edges causing latency and data misses in DET flip-flop applications
Solution Approach 1:
The clock gating circuit is segmented into separate paths for rising edges and falling edges. Each path has dedicated logic circuits (first digital logic circuit 110, second digital logic circuit 120) that independently process respective edge transitions, ensuring both edges are handled with appropriate timing without interfering with each other
Solution Approach 2:
An active-low latch circuit (115) acts as an intermediary between the first digital logic circuit and the second digital logic circuit. This latch circuit stores the select signal state and coordinates the switching between rising edge and falling edge processing, ensuring proper timing synchronization for dual-edge-triggered flip-flops
2Loss of energy
If conventional clock gating circuits are used with negative-edge-triggered flip-flops, then power consumption is reduced, but timing accuracy deteriorates on rising edges causing latency and data misses in DET flip-flop applications
Solution Approach 1:
The clock gating circuit is segmented into separate paths for rising edges and falling edges. Each path has dedicated logic circuits (first digital logic circuit 110, second digital logic circuit 120) that independently process respective edge transitions, ensuring both edges are handled with appropriate timing without interfering with each other
Solution Approach 2:
An active-low latch circuit (115) acts as an intermediary between the first digital logic circuit and the second digital logic circuit. This latch circuit stores the select signal state and coordinates the switching between rising edge and falling edge processing, ensuring proper timing synchronization for dual-edge-triggered flip-flops
3Loss of energy
If clock gating is applied to DET flip-flops, then power consumption is reduced, but latency increases due to delayed gated clock signal transitions
Solution Approach 1:
The logic circuits generate select signals and gated clock signals in advance of the actual edge transitions. The active-low latch circuit pre-stores the select signal state, and the second digital logic circuit prepares the inverted or non-inverted clock signal before the edge transition occurs, eliminating latency when the gated clock signal needs to change state
4Loss of energy
If clock gating is applied to DET flip-flops, then power consumption is reduced, but data misses occur due to missed rising or falling edge transitions
Solution Approach 1:
The clock gating circuit is segmented into separate paths for rising edges and falling edges. Each path has dedicated logic circuits (first digital logic circuit 110, second digital logic circuit 120) that independently process respective edge transitions, ensuring both edges are handled with appropriate timing without interfering with each other
Solution Approach 2:
The logic circuits generate select signals and gated clock signals in advance of the actual edge transitions. The active-low latch circuit pre-stores the select signal state, and the second digital logic circuit prepares the inverted or non-inverted clock signal before the edge transition occurs, eliminating latency when the gated clock signal needs to change state
Data Source
AI summary
Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.