Clock Conversion Circuit for Stable Variable-Frequency Memory Testing
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Solution Overview
Problem
Existing test systems for memory devices operate at speeds lower than the memory devices, limiting their ability to provide diverse clock signals required for various tests.
Innovation Solution
A clock conversion device with separate first and second clock generators, and a clock conversion circuit that generates a third clock signal by converting characteristics of the second clock signal, enabling the provision of clock signals with varying frequencies and characteristics to devices under test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single clock generator is used in existing test systems, then the device structure is simple, but the ability to provide diverse clock signals with varying frequencies is limited
Solution Approach 1:
The clock generator is divided into separate functional modules: a first clock generator for generating a base clock signal, a frequency multiplier for increasing the frequency, and a clock conversion circuit for converting the clock signal characteristics. This segmentation allows each module to perform its specific function efficiently while collectively providing diverse clock signals with varying frequencies to the DUT.
2Speed
If the test system operates at lower speed, then the system is more stable, but it cannot keep up with high-speed memory devices requiring various clock signals
Solution Approach 1:
The system dynamically adjusts clock signal characteristics by using a frequency multiplier that can vary the multiplication factor and a clock conversion circuit that can change clock signal properties. This dynamic capability allows the test system to operate at high speeds while adapting to different clock frequency requirements of memory devices during various test phases.
3Productivity
If clock signal frequency is increased for high-speed testing, then testing efficiency improves, but clock signal stability may be compromised
Solution Approach 1:
A buffer circuit is introduced as an intermediary between the frequency multiplier and the DUT to stabilize the high-frequency clock signal. The buffer circuit isolates the DUT from frequency variations and signal integrity issues, ensuring stable clock signal delivery even at high multiplication factors, thereby maintaining both testing efficiency and reliability.
Data Source
AI summary
A clock conversion device includes a first clock generator configured to receive a clock signal from a test device and generate a first clock signal with a fixed multiplied frequency, a second clock generator separated from the first clock generator and configured to receive a clock signal from the test device and generate a second clock signal with a varying multiplied frequency, and a clock conversion circuit configured to receive the second clock signal, generate a third clock signal by changing a frequency of the second clock signal, and provide the third clock signal to a device under test (DUT) that is a test target.