Multi-Bit Flip-Flop Gating for Low-Power Scan Test Output
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Solution Overview
Problem
Scan chains in flip-flops consume unnecessary power during test modes due to continuous operation of combinational logic circuits, leading to increased energy expenditure.
Innovation Solution
A multi-bit flip-flop design with a gating function that keeps data-out signals at a fixed voltage level during test modes and allows scan-out signals to change in response to test signals, reducing power consumption by disabling data-out stage circuits in test modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chains operate in test mode with data transmission enabled, then test signal can be transmitted through the scan chain, but unnecessary power consumption occurs due to continuous operation of combinational logic circuits
Solution Approach 1:
The patent implements dynamic control of the data-out stage circuits by introducing a test mode control signal that switches the operational state of these circuits. In test mode, the control signal disables the data-out stage circuits, preventing unnecessary signal transitions and reducing power consumption. In normal mode, the circuits operate normally to maintain data transmission functionality. This dynamic switching resolves the contradiction by adapting the circuit behavior to the operational mode.
Solution Approach 2:
The patent segments the flip-flop circuit into distinct functional blocks: the scan chain core, the data-out stage circuits, and the combinational logic circuits. By segmenting the data-out stage circuits as separate controllable units, the invention enables selective disabling of these segments during test mode while keeping the scan chain operational. This segmentation allows independent control of power-consuming segments without affecting the overall test functionality.
2Adaptability or versatility
If data-out stage circuits remain operational during test mode, then data transmission functionality is maintained, but signal transitions continue to occur causing increased energy expenditure
Solution Approach 1:
The invention applies dynamic control to the data-out stage circuits through a test mode control signal. When test mode is activated, the control signal dynamically changes the state of the data-out stage circuits to a disabled condition, preventing signal transitions and reducing energy expenditure. The circuits dynamically switch between operational and disabled states based on the mode control signal, resolving the contradiction between maintaining adaptability and reducing energy loss.
Solution Approach 2:
The patent extracts the data-out stage functionality from the main scan chain operation by providing separate control paths. The test mode control signal specifically targets and disables only the data-out stage circuits, extracting this particular function from the overall operational flow during test mode. This extraction allows the scan chain to continue operating for test purposes while removing the energy-consuming data transmission capability selectively.
3Ease of operation
If combinational logic circuits operate continuously to maintain data transmission, then data output functionality is preserved, but unnecessary power consumption increases during test procedures
Solution Approach 1:
The invention implements dynamic control of combinational logic circuits through the test mode control signal. During test mode, the control signal dynamically adjusts the operational state of the combinational logic circuits to minimize activity and reduce power consumption. In normal mode, these circuits operate continuously to maintain data output functionality. This dynamic adaptation resolves the contradiction between ease of operation and energy consumption by adjusting circuit activity based on operational requirements.
Solution Approach 2:
The patent applies preliminary anti-action by preemptively disabling the combinational logic circuits before unnecessary power consumption occurs. The test mode control signal is introduced early in the test mode activation process, preventing the combinational logic circuits from entering high-power states during test operations. This preliminary action counteracts the tendency of these circuits to consume power continuously, resolving the contradiction before the harmful effect manifests.
Data Source
AI summary
A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.