TDC Bubble Error Correction Using Majority Bit Evaluation

The patent implements a feedback mechanism where the TDC output is continuously monitored for bubble errors, and correction signals are generated and fed back to correct the erroneous bits. The error detection circuit monitors the TDC output and generates correction signals that are applied back to the digital signal, creating a closed-loop system that maintains signal accuracy despite using coarse TDC resolution.

The patent introduces an intermediary error correction circuit between the TDC and the phase locked loop. This intermediary component includes error detection logic that identifies bubble patterns and correction logic that generates appropriate correction signals. The intermediary processes the TDC output, corrects identified errors, and provides the corrected signal to subsequent stages, thereby isolating the TDC's quantization limitations from the critical phase measurement function.

The error correction circuit applies corrections locally and selectively rather than processing the entire signal uniformly. The correction logic targets only specific bit positions where bubble errors are detected, applying corrections only where needed. This localized approach minimizes the complexity of the correction circuit while maintaining signal accuracy, as the circuit does not need to process or modify all bits of the TDC output.

The patent changes the parameter representation of the error correction by using predefined correction patterns and lookup tables rather than complex real-time calculation. The error detection circuit identifies bubble patterns and maps them to predetermined correction signals, transforming a potentially complex correction problem into a simpler parameter substitution task. This parameter-based approach reduces the computational complexity and hardware requirements of the correction circuit.