MASH Delta-Sigma TDC for On-Chip PLL Phase Noise Measurement

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Solution Overview

Problem

Current methods for measuring phase noise in phase-locked loops (PLLs) are costly and complex, and high-speed probes face issues at high temperatures, while existing built-in self-test (BIST) circuits suffer from stability problems due to high-frequency input clocks, making them unsuitable for general PLL applications.

Innovation Solution

The implementation of a high-order delta sigma (ΔΣ) time-to-digital converter (TDC) with a MASH type configuration, which cascades multiple first-order ΔΣ TDCs to form a high-order ΔΣ TDC, allowing for phase noise measurement without requiring a high-frequency reference clock and avoiding stability issues, suitable for on-chip PLL phase noise measurement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high-speed probes are used for phase noise measurement, then measurement accuracy is improved, but cost increases and reliability deteriorates at high temperatures

Engineering Contradiction:

Improvephase noise measurement accuracyVSAvoidprobe reliability at high temperatures

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent creates a built-in self-test (BIST) circuit that copies the essential measurement functionality onto the PLL chip itself. Instead of using external high-speed probes, the BIST circuit generates test signals and measures phase noise internally, eliminating the need for fragile external probing while maintaining measurement accuracy through on-chip signal generation and detection

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The PLL device performs its own phase noise measurement through the integrated BIST circuit. The BIST circuit generates test clock signals, feeds them to the PLL, and measures the output phase noise without requiring external measurement equipment. This self-service approach eliminates reliability issues associated with external probes at high temperatures

Inventive Principle:

Principle #25Self-service

2Measurement precision

If 2nd-order delta sigma TDC is used for phase noise measurement, then noise shaping capability is improved, but stability deteriorates due to high-frequency input clocks

Engineering Contradiction:

Improvenoise shaping capabilityVSAvoidcircuit stability at high frequencies

Core Design Contradiction:

Measurement precisionVSStability of the object's composition

Solution Approach 1:

The patent segments the high-order delta sigma TDC into multiple cascaded 2nd-order stages. Each stage operates at a manageable frequency with its own noise shaping function, and the combined effect achieves high-order noise shaping performance. This segmentation maintains stability by avoiding the need for a single high-frequency high-order TDC while still providing superior noise shaping capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-stage time-domain approach to a multi-stage cascaded architecture. By adding the dimension of multiple cascaded stages, the system achieves high-order noise shaping without requiring high-frequency operation in a single stage, thus maintaining stability while improving measurement precision

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Measurement precision

If high-frequency input clock is used in BIST circuit, then phase noise measurement capability is improved, but adaptability deteriorates for general PLL applications

Engineering Contradiction:

Improvephase noise detection capabilityVSAvoidsuitability for general PLL applications

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The BIST circuit is designed with dynamic frequency scaling capability. The delta sigma TDC and associated circuitry can operate at different clock frequencies depending on the application requirements. For phase noise measurement, it uses optimized frequencies, while for general PLL operation, it adapts to standard frequencies, making the system versatile across different applications

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11555851B2Built-in self test circuit for measuring phase noise of a phase locked loop

Publication Date: 2023.01.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).