FPGA Input Timing Using Serializer Shift Registers
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Solution Overview
Problem
Maintaining time synchronization between low-cost multi-platform systems is challenging due to limitations in downstream sample clocks used in field-programmable gate arrays (FPGAs), resulting in ambiguities close to 10 nanoseconds.
Innovation Solution
A system comprising an FPGA with an input pad, an input serializer with x serializer shift registers, and an x-bit wide shift register, which determines the time of signal arrival by serializing the signal, outputting parallel data, and sampling it at a slower clock rate to achieve precise timestamping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If GPS strobes and clocks are used to maintain time synchronization, then time synchronization between systems is maintained, but timing precision is limited to ambiguities close to 10 nanoseconds
Solution Approach 1:
The patent segments the timing measurement process into multiple phases using x serializer shift registers, where each register captures the signal at a different time period. This segmentation allows the system to determine which specific time period the signal arrived during, reducing timing ambiguity from 10 nanoseconds to sub-nanosecond precision by dividing the measurement into discrete, measurable intervals
Solution Approach 2:
The patent introduces an intermediary x-bit wide shift register that acts as a buffer between the high-speed serializer clock and the lower-speed sampling clock. This intermediary structure allows precise timing information to be captured and held until it can be read by the lower-speed logic, enabling sub-nanosecond precision without requiring the entire system to operate at high speeds
2Productivity
If downstream sample clocks are used to sample input pins, then signal sampling is performed, but timing ambiguities close to 10 nanoseconds occur
Solution Approach 1:
The patent performs preliminary action by using the high-speed serializer clock to pre-sample the input signal through x serializer shift registers before the lower-speed sampling clock reads the data. This preliminary high-speed sampling captures the exact time period of signal arrival, and the result is then transferred to the lower-speed register for reading, achieving both high productivity and sub-nanosecond timing precision
Solution Approach 2:
The patent transitions from a single-dimension timing measurement (single clock domain) to a multi-dimensional approach by introducing x serializer shift registers that operate in the time domain at high speed while the sampling occurs at lower speed. This dimensional transformation allows the system to measure timing precision in one dimension (serializer clock periods) while maintaining productivity in another dimension (sampling rate)
Data Source
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AI summary
A system may include a field-programmable gate array, FPGA. The FPGA (104) may be configured to: determine a time corresponding to in which of x time periods a signal arrived at an input serializer (208) based at least on a value; and determine a time when the signal arrived at an input pad based at least on a shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer (208) based at least on the value.