Memory Scan Chain Latch Topology for Lower Test-Mode Power
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Solution Overview
Problem
Existing scan chain architectures suffer from high power consumption due to the overhead current consumption of D flip flops in both functional and test modes, which is undesirable for efficient testing of memory devices like flip flops or latches.
Innovation Solution
The proposed scan chain architecture incorporates low threshold voltage transistors for the master latch and standard threshold voltage transistors for the slave latch, with separate clocking mechanisms for functional and test modes, utilizing a multiplexer to select between functional and test inputs, thereby reducing power consumption without affecting functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard D flip flop architecture is used in scan chain, then testing functionality is achieved, but power consumption is high due to overhead current in both functional and test modes
Solution Approach 1:
The scan chain architecture is segmented into master latch and slave latch portions. The master latch uses LTVT transistors for continuous operation in both functional and test modes, while the slave latch uses STVT transistors activated only during test mode. This segmentation allows selective activation of power-consuming components based on operational mode, reducing overall power consumption while maintaining testing functionality.
Solution Approach 2:
The invention dynamically switches between functional mode and test mode operation by controlling the activation of slave latch clocks (S_F_CLK and S_T_CLK) only during test mode. The mode selection input dynamically reconfigures the multiplexer to route either functional logic input or test input to the master latch, enabling adaptive power consumption based on operational requirements.
2Speed
If LTVT transistors are used throughout the scan chain, then speed is improved, but power consumption increases due to higher leakage current
Solution Approach 1:
Different transistor types are applied to different portions of the scan chain based on local requirements. LTVT transistors with lower switching thresholds are used in the master latch where high-speed operation is critical for continuous functional and test mode operation. STVT transistors with higher threshold voltages are used in the slave latch where speed is less critical but power consumption must be minimized during test mode operation.
Data Source
AI summary
A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.