Configurable Test Logic for Post-Reset Subsystem Measurement
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Solution Overview
Problem
The existing Test Access Port (TAP) configuration method for computing devices is inadequate, as it cannot configure test logic until the device exits reset, leading to a race condition and a missed window for measuring subsystems during the initial reset phase.
Innovation Solution
A programmable device is used to detect a test mode request, obtain configuration information, and control the device to exit reset, allowing for testing during the critical time interval after reset, by leveraging existing communication interfaces and configuration information memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the existing TAP configuration method is used, then the test logic can be configured, but the configuration cannot occur until the device exits reset, causing a missed window for measuring subsystems during the initial reset phase
Solution Approach 1:
The patent applies preliminary action by enabling test logic configuration to occur before the device exits reset. The configuration is performed during the reset phase using a configuration interface that remains accessible during reset, allowing the test logic to be prepared in advance. This eliminates the race condition and ensures the configuration is complete before the measurement window begins, capturing the critical initial reset phase that was previously missed.
2Productivity
If the device exits reset before test logic configuration is complete, then the device can operate normally, but the test logic cannot measure subsystems during the critical initial reset phase
Solution Approach 1:
The configuration is performed preliminarily during the reset phase before the device exits to normal operation. This allows the test logic to be fully configured and ready to capture subsystem measurements during the critical initial reset phase, ensuring both testing efficiency and measurement precision are maintained.
Solution Approach 2:
The patent introduces a configuration interface as an intermediary that remains accessible during the reset phase. This intermediary enables the configuration data to be transferred to the test logic even when the device is in reset state, bridging the gap between the need for early measurement and the requirement for proper configuration.
3Ease of operation
If the configuration is performed after reset exit, then the device is fully operational, but the race condition causes the measurement window to be missed
Solution Approach 1:
The configuration is performed preliminarily during reset rather than after reset exit. This preliminary configuration approach maintains ease of operation by using a straightforward configuration interface while simultaneously preventing the loss of measurement opportunity by ensuring configuration is complete before the device exits reset and begins normal operation.
Solution Approach 2:
The system performs self-service by automatically capturing the configuration data during the reset phase without requiring external intervention to delay or coordinate the reset exit. The test logic independently receives its configuration and is ready to measure subsystems as soon as the device exits reset, eliminating the race condition while maintaining operational simplicity.
Data Source
AI summary
In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.