Clock-Synchronized Failure Detection Circuit for Fault Injection Attacks
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Solution Overview
Problem
Existing semiconductor devices are unable to accurately detect failures caused by fault injection attacks, which can lead to security risks and unintended operations.
Innovation Solution
A failure detection circuit is implemented in the semiconductor device, comprising a first detection circuit, a second detection circuit, and a comparator that operate in synchronization with a clock signal to compare detection results, allowing for the accurate identification of failures, including those induced by external attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only security risk reduction measures are taken, then security risk is reduced, but failure detection capability is insufficient
Solution Approach 1:
The patent creates a duplicate detection circuit that mirrors the original detection circuit's functionality. Both circuits process the same input signals independently, and their outputs are compared to detect discrepancies. This copying approach enables accurate failure detection while maintaining security risk reduction, as the redundant circuit can identify tampering or faults in the original circuit.
Solution Approach 2:
The patent implements a feedback mechanism where the outputs of both detection circuits are fed into a comparison circuit. The comparison result is then used to generate an error signal that indicates whether a failure has occurred. This feedback loop continuously monitors the system state and provides real-time failure detection, resolving the contradiction between security risk reduction and failure detection capability.
2Measurement precision
If a failure detection circuit with multiple detection circuits and comparators is added, then failure detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the detection function into separate modular components: detection circuits, comparison circuits, and error signal generation circuits. Each module performs a specific function independently, making the overall system easier to design, implement, and maintain despite the increased complexity. The segmentation allows for systematic integration of multiple detection circuits without creating monolithic complexity.
Solution Approach 2:
The detection circuits and comparison circuits are designed with universal functionality that can handle multiple detection scenarios. The same circuit architecture can detect various types of failures including tampering, external interference, and internal faults. This multi-functionality reduces the need for separate specialized circuits for each detection scenario, thereby limiting the increase in device complexity while maintaining high detection accuracy.
Data Source
AI summary
A failure detection circuit is provided in the target circuit having a first circuit area for operating in synchronization with the first clock signal, a first detection circuit for outputting a first detection result obtained by transitioning the voltage level in synchronization with the first clock signal, the first clock signal a second detection circuit for outputting a second detection result obtained by transitioning the voltage level in synchronization with, and a first comparison circuit for outputting a first comparison result by comparing the first detection result and the second detection result. Accordingly, by the failure detection circuit, it is possible to detect the failure accurately.