Integrated Circuit At-Speed Clocking With Variable Capture Pulses
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Solution Overview
Problem
Existing at-speed testing methods for integrated circuits (ICs) are limited by the use of fixed clock pulses during the capture phase, which restricts fault coverage and test quality, and requires a large clocking system due to the need for storing configuration values for each possible operating frequency.
Innovation Solution
An electronic circuit board with an integrated circuit (IC) and a test circuit that generates a test clock signal with variable clock pulses, recorded by a recording circuit and replayed at the desired operating frequency by a clocking system, allowing for dynamic configuration and improved test pattern generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed clock pulses are used during the capture phase, then the clocking system can be simplified, but fault coverage and test quality are restricted
Solution Approach 1:
The patent implements dynamic clock pulse generation during the capture phase, where the number of clock pulses is no longer fixed but can be varied based on test requirements. The system uses a counter and control logic to generate a variable number of clock pulses (e.g., 1 to 64 pulses) during capture phase, allowing flexible testing while maintaining a relatively simple clocking system structure.
2Adaptability or versatility
If configuration values for each operating frequency are stored, then the IC can operate at multiple frequencies, but the clocking system size increases
Solution Approach 1:
The patent pre-calculates and stores division ratios rather than full configuration values for each frequency. The system uses a lookup table that stores only the essential division ratio information needed for frequency synthesis, reducing the storage requirements compared to storing complete configuration sets for each operating frequency.
Solution Approach 2:
The system uses a reference clock signal and generates operating frequencies by copying and dividing the reference clock. Instead of storing complete frequency synthesis configurations, the system copies the reference clock and applies division ratios from a compact lookup table, significantly reducing the clocking system size while maintaining multi-frequency operation capability.
3Reliability
If a variable number of clock pulses is generated during capture phase, then test quality improves, but the clocking system becomes more complex
Solution Approach 1:
The clocking system is segmented into distinct functional modules: a phase-locked loop (PLL) for frequency synthesis, a counter for pulse counting, a lookup table for division ratios, and control logic for phase selection. This segmentation allows each module to perform a specific function independently, making the overall system more manageable and easier to implement despite the variable pulse generation capability.
Solution Approach 2:
The patent introduces an intermediary counter and control logic that mediates between the fixed reference clock and the variable capture phase requirements. The counter acts as an intermediary that translates the fixed reference clock into a variable number of capture clock pulses based on the stored division ratios, adding functionality without significantly increasing overall system complexity.
Data Source
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AI summary
An integrated circuit (IC), including a recording circuit and a clocking system, is provided. During a capture phase of an at-speed testing of the IC, the recording circuit records a number of clock pulses of a test clock signal and generates configuration data indicative of the recorded number of the clock pulses. The clocking system receives a reference clock signal and the configuration data and generates an at-speed clock signal. During the capture phase, the at-speed clock signal includes clock pulses that are extracted from the reference clock signal based on the configuration data. A count of the extracted clock pulses is equal to the recorded number of clock pulses of the test clock signal. The at-speed testing of the IC is enabled based on the at-speed clock signal.