Memory Controller Test Circuitry for 3D-IC Timing Measurement
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Solution Overview
Problem
Integrated circuit (IC) devices in directly attached configurations, such as 3D-ICs, pose challenges in testing input and output timing parameters due to inaccessible pins, making it difficult to ensure proper operation, especially when directly attached to another IC device.
Innovation Solution
Incorporating an internal test signal generator and test signal wires that allow for precise adjustment of clock and data signals, enabling the measurement of timing parameters like setup and hold times without impacting global clock signals, thereby isolating and testing individual IC dies separately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If IC devices are directly attached in 3D-IC configuration, then integration density and compactness are improved, but accessibility of pins for testing deteriorates
Solution Approach 1:
The patent introduces an intermediary testing mechanism where test signals are injected into internal nodes of the IC device through existing functional interfaces. This mediator approach allows external test equipment to access internal timing parameters without physically accessing the inaccessible pins, thus resolving the contradiction between compact integration and test accessibility.
Solution Approach 2:
The patent creates a virtual model of the signal paths by injecting test signals and measuring their propagation through the device. Instead of directly accessing physical pins, the system copies the behavior of actual signal paths through controlled test signal injection and observation at accessible interfaces, enabling indirect measurement of timing parameters.
2Measurement precision
If test signals are injected into internal nodes, then measurement precision of timing parameters is improved, but device complexity increases
Solution Approach 1:
The patent designs the test signal injection mechanism to utilize existing functional interfaces of the IC device, making the test circuitry multi-functional. The same interfaces used for normal device operation are also employed for test signal injection and observation, eliminating the need for dedicated test-only interfaces and reducing overall device complexity while maintaining measurement precision.
Solution Approach 2:
The IC device is designed to be self-testable through its own functional interfaces. The device uses its existing signal paths, latches, and logic elements to propagate and indicate test signals, eliminating the need for external complex test equipment directly accessing internal nodes. The device essentially tests itself using its own operational mechanisms.
Data Source
AI summary
A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.