Clock Shaper Synchronization for 2 GHz Transition Fault Testing
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Solution Overview
Problem
Traditional stuck-at fault tests are inadequate for detecting defects like high impedance metal, high impedance shorts, and cross talk in deep sub-micron CMOS technology, which manifest as timing failures during at-speed tests, and existing clock shaper circuits with FSMs or PLLs fail to synchronize scan enable signals with clock pulses at frequencies above 1.2 GHz, impeding effective transition fault testing.
Innovation Solution
A clock shaper circuit with a synchronizing circuit, clock leaker circuit, and multiplexer that provides synchronized clock pulses at frequencies up to 2 GHz, using shift registers and multiplexers to ensure the scan enable signal is synchronized with clock pulses, reducing logic depth and enabling effective at-speed transition fault testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clock shaper circuits with FSMs or PLLs are used, then circuit functionality is provided, but synchronization of scan enable signals with clock pulses fails at frequencies above 1.2 GHz
Solution Approach 1:
The patent extracts the synchronization function from complex FSM/PLL circuits and implements it separately using scan enable signals that directly control clock pulse generation. This separation allows the clock shaper circuit to operate at high frequencies (up to 2 GHz) while maintaining reliable synchronization between scan enable signals and clock pulses through direct signal coupling rather than complex state machine control.
Solution Approach 2:
The scan enable signal is used in advance to pre-synchronize the clock pulse generation timing. By using the scan enable signal that already exists in the test architecture to control the clock shaper circuit, the patent ensures that clock pulses are generated at the correct time relative to scan operations, enabling reliable synchronization at high frequencies without requiring complex feedback control.
2Productivity
If deep sub-micron CMOS technology is used, then area, power, and performance metrics are improved, but detection of defects like high impedance metal and cross talk becomes difficult
Solution Approach 1:
The patent applies periodic clock pulses generated by the clock shaper circuit to systematically excite and test signal transitions through the circuit under test. By providing precisely timed periodic clock signals at high frequencies (up to 2 GHz), the test architecture can detect timing-related defects such as high impedance metal and cross talk that manifest only during at-speed operation, overcoming the detection difficulties in deep sub-micron technology.
3Speed
If clock pulses are provided without synchronization, then circuit speed is maintained, but transition fault testing effectiveness is impeded
Solution Approach 1:
The scan enable signal serves as an intermediary that couples the test control logic with the clock pulse generation. This intermediary signal ensures that clock pulses are generated at the correct moments in the test sequence while maintaining high-frequency operation. The clock shaper circuit uses this intermediary signal to synchronize clock pulse timing, thereby maintaining both high speed and testing accuracy for transition fault detection.
Data Source
AI summary
An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.